24-02-09

Implementing RTOS (xilkernel) on Xilinx Spartan 3E Starter board

I have just published an tutorial on howto implement the xilkernel (sometimes called XMK) v4.0 on the Xilinx Spartan 3E Starter board. This xilkernel is a Real-Time Operating System (RTOS)

 

 

have fun...

 

you can also find an Round Robin Application in the rar files that is included with the tutorial...

 

http://pwo.fpga.be/RTOS/

13:53 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (3) | Tags: rtos, microblaze, fpga, softcore, xilinx, 32-bit, spartan 3e, spartantan |  Facebook |

08-04-08

XIOS Hogeschool Limburg uses LabVIEW and LabVIEW FPGA to teach FPGA Applications class

Link: http://zone.ni.com/devzone/cda/tut/p/id/7154

 

More information: http://pwo.fpga.be/

 

 

 

09:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: labview fpga, fpga, classroom, digital electronics, xilinx |  Facebook |

05-03-08

7-segment Display on Xilinx SPARTAN3E Starter board with LabVIEW FPGA

This Application show an LabVIEW VI that is working as a driver for a 7-segment display.

project weblink:
http://decibel.ni.com/content/docs/DOC-1407;jsessionid=82a40f1930d9ca4239899c184ad6a899bef577ef252d.e38MaNyPaNePaO0Lch8Lax8Kc38Le6fznA5Pp7e

code weblink:
http://decibel.ni.com/content/servlet/JiveServlet/download/1407-2-1586/FPGA%20VI%207%20SEGMENT.zip

Requirements: Application Software: LabVIEW Professional Development System 8.5 Addon Software: LabVIEW FPGA Module 8.5

I developed this Application on my Xilinx SPARTAN3E Starter Board. I used a Kingbright SA52-11 7-segment display.

Enjoy

29-01-08

VGA Controller on SPARTAN3E starter board

You can download an example project for the SPARTAN3E starter board on this website: http://www.mobile-it.be/projects.php

 

Direct link: http://pwo.fpga.be/IP/Mobile_it_be_VGA_driver.rar

 

28-12-07

Running Counter on SPARTAN3E Starter Board by use of LabVIEW FPGA

Ok, I just created a next example for the Spartan3E starter board. It is a running binary counter that I send to the LED's.

 Screenshots:

countercontrol

 

counterblock
Just try to rebuild it; if you are not able to rebuild I am willing to send my bitfile to you.

 

Happy LabVIEW FPGA coding!

27-12-07

Interaction PC <--> SPARTAN3E starter board in LabVIEW


Here you can see the screenshot of a project I created to show how easy it is to create interaction between a PC and a XILINX SPARTAN3E starter board:

Project Managment  View:

SPLVPV

 

 

HOST VI:

hostvi                                                  

FPGA VI:

fpgavi

 

Download the full project here

 

Be sure to read the full disclaimer of LabVIEW FPGA before starting to develop applications.

18-12-07

ESL with LabVIEW FPGA

Today I experimented with LabVIEW FPGA targetting the Spartan3E University board. I worked all the projects out that where included in the pdf file you can get on the academic website of NI (National Instruments - http://www.ni.com ).

I have made:

* the LED example

* the LCD example

* the Switch example where you start from a empty project

* including an Xilinx ISE generated FIR filter (IP core integrating into LabVIEW FPGA) with this example I had some problems because the value of the signal that I sended to the ADC was not the correct value that was shown on my PC screen.

 

Links that could be handy:

* Spartan3E user guide of the starter board:

http://www.xilinx.com/support/documentation/boards_and_ki...

* download Spartan3E LabVIEW FPGA driver

http://digital.ni.com/express.nsf/bycode/spartan3e

* WORD version of the LabVIEW FPGA tutorial for the Spartan3E starter university board (for easy copy/pasting of the VHDL code for the IP core that has to be implemented :-) )

http://etidweb.tamu.edu/ftp/ENTC219/LabView/Getting%20Sta...

enjoy!

12-12-07

Program your Spartan 3E FPGA board with LabVIEW

Hi FPGA World,

ready for a new sensation that will in the next years rule the world of ESL (electronic system-level ) FPGA programming?

I just received my Academic Newsletter from NI.com (National Instruments the makers of LabVIEW and LabVIEW FPGA).

They introduced recently a driver for using LabVIEW to program your FPGA Silicon on the Xilinx Spartan 3E starter board.

 In this document they describe a way to program the FPGA boards LED's, LCD and a custom made Xilinx Spartan 3E LabVIEW project. They even show you how to integrate VHDL code into a Spartan 3E LabVIEW Project.

 

For people who can't wait and want to start graphically programming their FPGA's you can download everything here: http://digital.ni.com/express.nsf/bycode/spartan3e

Be sure that the people who download this driver and tutorial are all academic people .... read the license...

17:58 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: esl, labview fpga, project, vhdl, lcd, silicon, xilinx, spartan3e |  Facebook |

20-11-07

FPGA from Scratch

Just found a good blog for anyone starting with Xilinx FPGA's (EDK,...)

 

check out:

http://svenand.blogdrive.com/archive/40.html

 

enjoy!

16:26 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, edk, scratch, start, xilinx |  Facebook |

21-03-07

Success with IMEC and Synplicity's Synplify® Premier Software

 
 

 


Success with IMEC and Synplicity's Synplify® Premier Software
Click here to learn more about the Synplify Premier tool.

 
IMEC, a European nanoelectronics research institution, used Synplify Premier software from Synplicity to demonstrate that its C-programmable reconfigurable processor architecture ADRES is feasible for use in portable wireless multimedia devices. The entire processor system was successfully prototyped for a multimedia ADRES processor instance on a Xilinx Virtex-4 FPGA through use of the Synplify Premier tool. The Synplify Premier product provided excellent support for achieving the required clock frequency. IMEC credits the Synplify Premier tool's built-in knowledge of the FPGA's physical characteristics for the accurate timing results that it delivers. The ADRES prototype system has been important for IMEC in showing that the ADRES processor architectural template and its corresponding C-compiler are sufficiently stable for use in portable devices. 
 
 
IMEC's ADRES Innovation Promises a New Future for Hand-held Multimedia Devices
 
IMEC of Leuven, Belgium is one of the world's leading independent research institutions in nanoelectronics and nanotechnology. Its research focuses on next generation chips and systems, and bridges the gap between university research and technology development in industry. IMEC's blend of know-how and corporate relationships position the organization to help shape key technologies for future systems. 
 
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) contains two views which are tightly coupled: an array of processing elements that runs the data flow part of the application and a VLIW that executes the control. For hand-held multimedia devices, this technology delivers enormous flexibility benefits over fixed ASICs because various video codec standards can be quickly and easily accommodated through C programming. In addition, ADRES-based processors offer power efficiencies six to twelve times higher than state-of-the-art C-programmed processors. 
 
With the demonstration IMEC has proven that processors based on the ADRES architecture can deliver sufficient performance. The multimedia ADRES processor instance was developed to support MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. The demonstration employed the HAPS-32 from HARDI Electronics, which contains two Xilinx Virtex-4 LX200 FPGAs, as its prototyping board. IMEC constrained the FPGA clock input to 50 MHz to decode 30 frames/sec of H.264/AVC content at CIF resolution. 
 
Synplify Premier Tool Delivers the Necessary Performance 
 
IMEC began by synthesizing the design using the Synplify Pro product from Synplicity, the tool that had served the organization well for many years. Synplify Pro software came close to the goal at 46 MHz, but not close enough. 
 
"It was essential that we find a way to reach 50 MHz, and so we performed an investigation of the state of the art in FPGA synthesis," said Maryse Wouters, Activity Leader of the Integration Team. "Fortunately we found our answer, the Synplify Premier solution, which is capable of delivering the performance we needed. In fact it did even better than we had hoped, 52.6 MHz. Everyone was pleased with the performance gain."
 
"The reason why the Synplify Premier tool does the job better is that it understands the physical characteristics of the FPGA in fine detail and uses that knowledge to craft an optimal design," explained Wouters. "That's particularly important with the most advanced FPGAs on the market." 
 
Building on Synplify Pro technology, the Synplify Premier solution embodies its knowledge of an FPGA's specifics through a patented Synplicity technique called graph-based physical synthesis, which represents an FPGA's pre-existing wires, switches, and placement sites as a detailed routing resource graph. Graph-based physical synthesis produces rapid timing closure by automatically outputting timing-correlated legal placement and by considering availability of actual FPGA routing resources when measuring delays, rather than just physical proximity of instances. Unlike ASICs, in an FPGA physical proximity does not always correlate to timing delays, making ASIC-style physical synthesis approaches inaccurate when applied to FPGAs. Only graph-based physical synthesis can accurately estimate timing delays when performing physical synthesis.   
 
Graph-based physical synthesis also cut place-and-route runtimes significantly for IMEC. The total elapsed time for placement and routing was six hours with the Synplify Premier solution versus seventeen hours with the Synplify Pro tool. The reason is that in addition to performing synthesis, the Synplify Premier product actually places the design in a manner known to meet timing, and delivers a design that will be fully routable using the Xilinx ISE toolset. 
 
The correlation between the Synplify Premier solution's performance predictions and actuals was much better than IMEC had seen. The new tool predicted 51 MHz performance, which was very close to the actual result of 52.6 MHz.
 
IMEC's New Standard for Synthesizing 90 nm FPGAs and Below
 
With its flexibility to incorporate multiple video codec standards, the short time-to-market made possible by its high level language programmability, and its power efficiency, ADRES promises to play a major role in the next generation of mobile multimedia platforms. 
 
"Using an FPGA-based prototype platform, IMEC has demonstrated its C-programmable multimedia ADRES processor instance for real time H.264/AVC video decoding," said Wouters. "The performance gain that the Synplify Premier solution delivered was as promised in the Synplify Premier data sheet." 
 
Because of the excellent results it delivers, the Synplify Premier product has now become part of the tool flow at IMEC for future projects using leading edge FPGAs. "It is clear that for 90 nm FPGAs and beyond, the timing closure offered by the Synplify Premier tool is crucial," Wouters concluded. 
 
Click here to learn more about the Synplify Premier tool.

10-12-06

FPGA Based RFID reader

I just found online a nice article about building your own FPGA based RFID card reader. For more information visit the following link:

 

http://www.cieonline.co.uk/cie2/articlen.asp?pid=1404&...

 

 

12:50 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, xilinx, lineair, rfid, microblaze, http, server |  Facebook |

04-12-06

FPGA start-ups will struggle, says Xilinx CEO Wim Roelants

http://www.electronicsweekly.com/ARTICLES/2006/11/30/4025...

 

Nice story but: Electronic Engineers all over the world: you know what they say: If a professional says you can't make it you have to make it to become a guru :)

 

 

 

20:25 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: xilinx, ceo, fpga, start-ups, silicon |  Facebook |