12-12-07

Program your Spartan 3E FPGA board with LabVIEW

Hi FPGA World,

ready for a new sensation that will in the next years rule the world of ESL (electronic system-level ) FPGA programming?

I just received my Academic Newsletter from NI.com (National Instruments the makers of LabVIEW and LabVIEW FPGA).

They introduced recently a driver for using LabVIEW to program your FPGA Silicon on the Xilinx Spartan 3E starter board.

 In this document they describe a way to program the FPGA boards LED's, LCD and a custom made Xilinx Spartan 3E LabVIEW project. They even show you how to integrate VHDL code into a Spartan 3E LabVIEW Project.

 

For people who can't wait and want to start graphically programming their FPGA's you can download everything here: http://digital.ni.com/express.nsf/bycode/spartan3e

Be sure that the people who download this driver and tutorial are all academic people .... read the license...

17:58 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: esl, labview fpga, project, vhdl, lcd, silicon, xilinx, spartan3e |  Facebook |

21-10-07

Nice Hobby Electronic projects for the weekends ;-)

I just found 2 nice projects for everyone related to software or hardware projects:

 

http://wiki.openbeacon.org/wiki/OpenBeacon_USB

http://www.openbeacon.org/ --> RfID receiver !!!

 

http://lekernel.lya.eu/ula.html --> Logic Analyzer USB2.0 and FPGA based!

 

Check them out dudes, they are really cool!

 

 

 

12:12 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: usb, vhdl, fpga, rfid |  Facebook |

03-10-07

VHDL Project for LCD

I just found the next interesting article on controlling an LCD from an FPGA board by use of VHDL check out this link:

 

http://www.xess.com/projects/LCD_HD44780.pdf

design files: http://www.xess.com/projects/LCD_HD44780.ZIP

 

enjoy ;-)

17:06 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: vhdl, lcd, example, fpga, article |  Facebook |

14-06-07

VHDL code for an 74-series ALU (the 74LS381 chip)

Hereby I give you my code of the 74LS381 IC, which is an ALU with 4-bits width.

 

The VHDL Code:

-- IC74381.vhd
-- Developed by Vincent Claes
-- claesvincent (at) gmail.com

-- http://mobile.skynetblogs.be
-- 2007 (c)
--
-- This version is a simlified version of the 74LS381 IC. It shows the main functionality in VHDL
-- It is developed for educational purposes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  s2  s1  s0  operation
--------------------------
--  L   L   L   clear
--  L   L   H   B minus A
--  L   H   L   A minus B
--  L   H   H   A plus B
--  H   L   L   A xor B
--  H   L   H   A + B
--  H   H   L   AB
--  H   H   H   PRESET  

entity IC74381 is
port(   a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        s: in std_logic_vector (2 downto 0);
        f: out std_logic_vector (3 downto 0)
);
end IC74381;

architecture arch of IC74381 is
signal BminusA,AminusB,AplusB,AxorB,AandB,AB: std_logic_vector(3 downto 0);
signal au,bv0,bv1,bv2,bv3: unsigned(3 downto 0);
signal p0,p1,p2,p3,prod: unsigned(7 downto 0);

begin

BminusA <=  std_logic_vector(signed(b)-signed(a));
AminusB <=  std_logic_vector(signed(a)-signed(b));
AplusB  <=  std_logic_vector(signed(a)+signed(b));
AxorB   <= a xor b;
AandB   <= a and b;

au  <=unsigned(a);
bv0 <=(others=>b(0));
bv1 <=(others=>b(1));
bv2 <=(others=>b(2));
bv3 <=(others=>b(3));
p0  <="0000" & (bv0 and au);
p1  <="000"&(bv1 and au) & "0";
p2  <="00" & (bv2 and au) & "00";
p3  <="0" & (bv3 and au) & "000";
prod<=((p0+p1)+(p2+p3));
AB<=std_logic_vector(prod(3 downto 0));

f   <=  "0000"      when s="000" else
        BminusA     when s="001" else
        AminusB     when s="010" else
        AplusB      when s="011" else
        AxorB       when s="100" else
        AandB       when s="101" else
        AB          when s="110" else
        "1111"; 
end arch;

 

 

The testbench code:

 

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    a : inout std_logic_vector(3 downto 0) := x"7";
    b : inout std_logic_vector(3 downto 0) := x"3";
    s : inout std_logic_vector(2 downto 0));

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 10 ns;
    s <= "101";
    wait for 10 ns;
    s <= "110";
    wait for 10 ns;
    s <= "111";
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 20 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal a : std_logic_vector(3 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal s : std_logic_vector(2 downto 0);
  signal f : STD_LOGIC_VECTOR(3 downto 0);

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (a => a,
              b => b,
              s => s);

  -- Instantiation of Model Under Test.
  IC74381_0 : entity work.IC74381
    port map (a => a,
              b => b,
              s => s,
              f => f);
end tbGeneratedCode;

 

Screenshot of the Simulation in ModelSim:

 

wave_IC74381

 

Please remember this code is written in 4bits width. And I show the results in HEX!!!

 

For educational purposes I also include the netlist view of my program:

 

netlistview_IC74381

 

13-06-07

VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )

 

-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
 port(
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
  );
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

begin
output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;

 

Here is the code for a simple testbench:

 

-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;

 

I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.

 

I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:

 

even_detector

13:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: synplify, fpga, libero ide, example, modelsim, vhdl, hardware, programming, actel, actl |  Facebook |

16-03-07

VHDL code for 7segment display

For some of your FPGA projects it can be usefull to get an 7-segment display driver circuit. There is no 7-segment LCD on my ACTEL fpga boards but I am sure you guys know how to work around this topic with your hands ;-)

 

 

VHDL code listing:

 

LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY seg7 ISPORT (
D       : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);  -- BCD input      
S       : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- 7 segment outputsEND seg7;
ARCHITECTURE display OF SEG7 ISBEGINs <=  	"1000000" WHEN d = "0000" ELSE       
      	"1111001" WHEN d = "0001" ELSE       
	"0100100" WHEN d = "0010" ELSE       
	"0110000" WHEN d = "0011" ELSE       
	"0011001" WHEN d = "0100" ELSE       
	"0010010" WHEN d = "0101" ELSE       
	"0000010" WHEN d = "0110" ELSE       
	"1111000" WHEN d = "0111" ELSE       
	"0000000" WHEN d = "1000" ELSE       
	"0010000" WHEN d = "1001" ELSE       
	"0001000" WHEN d = "1010" ELSE       
	"0000011" WHEN d = "1011" ELSE       
	"1000110" WHEN d = "1100" ELSE       
	"0100001" WHEN d = "1101" ELSE       	
	"0000110" WHEN d = "1110" ELSE       
	"0001110";                     
END display;

13:05 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: fpga, vhdl, actel, 7-segment |  Facebook |

12-03-07

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

Link: http://www.fpgajournal.com/news_2007/03/20070312_03.htm

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of CoVer™, a Windows®-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7™ core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance

Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop

The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

Components

The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

* Aldec Active-HDL (Designer Edition) mixed-language simulator
* Actel’s CoreConsole IP Deployment Platform
* Actel Libero® Integrated Design Environment (IDE) – Gold edition
* Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
* Software development system, including Actel’s SoftConsole program development environment

Availability

CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com.

About Aldec

Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com.

CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

22:09 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, actl, co-verification, actel, fpga, hw sw, asic, vhdl |  Facebook |

27-02-07

Running Led Continious Mode

Hi all,

 

If you want to expand the latest project 'running led' to continious mode this is very easy to do:

 

just do the following things: in your 'root vhdl file' change the following lines of code:

 

entity ARM7BOARD_CoreABC_EXPERIMENT is
    -- Port list
    port(
        -- Inputs
        PCLK : in std_logic;
        -- Outputs
        IO_OUT : out std_logic_vector(7 downto 0)
    );
end ARM7BOARD_CoreABC_EXPERIMENT;

 

Where the inputs are listed remove the NSYSRESET input.

 

In the Code also change the Port Map of the RTL code (look at the line NSYSRESET; I force it to be 1 that's the trick ):

-- Port map
        port map(
            -- Inputs
            INITADDR => (others => '0'),
            INITDATA => (others => '0'),
            INITDATVAL => '0',
            INITDONE => '0',
            INTREQ => '0',
            IO_IN => (others => '0'),
            NSYSRESET => '1', -- I removed: NSYSRESET => NSYSRESET,
            PCLK => PCLK,
            PRDATA => (others => '0'),
            PREADY => '1',
            -- Outputs
            INTACT => open,
            IO_OUT => IO_OUT,
            PADDR => open,
            PENABLE => open,
            PRESETN => open,
            PSEL => open,
            PWDATA => open,
            PWRITE => open
        );

 

 

Connect the Clock to pin W17 and the IO to the 8 led's on the board.

 

Have fun with it

09:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, vhdl, example, program, sample |  Facebook |

04-02-07

Working with Google Codesearch

Hi all,

 

ready for some geek google stuff?

 

there is a searchengine called 'Google Code Search' where you as a  developer in the electronic world can get many help from ( or ideas ) Here a few examples:

 

go to this website: http://www.google.com/codesearch

type: SPI lang:vhdl

quicklink: http://www.google.com/codesearch?q=SPI+lang%3Avhdl&hl...

 

and there you go, the VHDL code for an SPI interface.

 

Whatch the following example: Hello world for C++:

http://www.google.com/codesearch?hl=nl&lr=&q=hell...

 

enjoy this feature of google!

12:24 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: google, c, vhdl, codesearch, spi interface |  Facebook |

06-01-07

Learn SystemC for developing FPGA applications

Hi all,

 

today I got myself the informaiton and tools to study SystemC for developing FPGA applications. For now I have only one problem for getting into this material and that is one big missing in my life: TIME!!!!

 

Here are the links where you can download and learn some SystemC tricks:

* Tutorials (blog): http://sclive.wordpress.com/tag/sytemc-tutorials/

* Tutorial (website): http://www.asic-world.com/systemc/index.html

* LiveCD for SystemC: http://www.esperan.com/livecd/index.html

This liveCD includes a tutorial from Esperan. They are a real good point to start with SystemC.

 

If you have developed some SystemC applications or have found other tutorials can you please post this as a reaction to this post?

 

thanks in advance you blog readers!

 

* by the way there is also a good tutorial on VHDL on one of those website check this out: http://www.asic-world.com/vhdl/index.html

 

12:17 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: systemc, fpga, esperan, time, livecd, vhdl |  Facebook |

04-11-06

7-segment display LabVIEW VI

Here you find a VI that I have created in LabVIEW for educational purposes. It makes use of a FSM to have a working of a 7-segment display counter.

 

 

I hope this is usefull for some people who are visiting this blog... Soon more LabVIEW VI's available here...

 

Download here the source code 7-segmentSM.vi

 

 

 

14:35 Gepost door Mobile blogger in Web | Permalink | Commentaren (0) | Tags: vhdl, labview, dsp, fpga |  Facebook |