14-06-07

VHDL code for an 74-series ALU (the 74LS381 chip)

Hereby I give you my code of the 74LS381 IC, which is an ALU with 4-bits width.

 

The VHDL Code:

-- IC74381.vhd
-- Developed by Vincent Claes
-- claesvincent (at) gmail.com

-- http://mobile.skynetblogs.be
-- 2007 (c)
--
-- This version is a simlified version of the 74LS381 IC. It shows the main functionality in VHDL
-- It is developed for educational purposes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  s2  s1  s0  operation
--------------------------
--  L   L   L   clear
--  L   L   H   B minus A
--  L   H   L   A minus B
--  L   H   H   A plus B
--  H   L   L   A xor B
--  H   L   H   A + B
--  H   H   L   AB
--  H   H   H   PRESET  

entity IC74381 is
port(   a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        s: in std_logic_vector (2 downto 0);
        f: out std_logic_vector (3 downto 0)
);
end IC74381;

architecture arch of IC74381 is
signal BminusA,AminusB,AplusB,AxorB,AandB,AB: std_logic_vector(3 downto 0);
signal au,bv0,bv1,bv2,bv3: unsigned(3 downto 0);
signal p0,p1,p2,p3,prod: unsigned(7 downto 0);

begin

BminusA <=  std_logic_vector(signed(b)-signed(a));
AminusB <=  std_logic_vector(signed(a)-signed(b));
AplusB  <=  std_logic_vector(signed(a)+signed(b));
AxorB   <= a xor b;
AandB   <= a and b;

au  <=unsigned(a);
bv0 <=(others=>b(0));
bv1 <=(others=>b(1));
bv2 <=(others=>b(2));
bv3 <=(others=>b(3));
p0  <="0000" & (bv0 and au);
p1  <="000"&(bv1 and au) & "0";
p2  <="00" & (bv2 and au) & "00";
p3  <="0" & (bv3 and au) & "000";
prod<=((p0+p1)+(p2+p3));
AB<=std_logic_vector(prod(3 downto 0));

f   <=  "0000"      when s="000" else
        BminusA     when s="001" else
        AminusB     when s="010" else
        AplusB      when s="011" else
        AxorB       when s="100" else
        AandB       when s="101" else
        AB          when s="110" else
        "1111"; 
end arch;

 

 

The testbench code:

 

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    a : inout std_logic_vector(3 downto 0) := x"7";
    b : inout std_logic_vector(3 downto 0) := x"3";
    s : inout std_logic_vector(2 downto 0));

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 10 ns;
    s <= "101";
    wait for 10 ns;
    s <= "110";
    wait for 10 ns;
    s <= "111";
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 20 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal a : std_logic_vector(3 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal s : std_logic_vector(2 downto 0);
  signal f : STD_LOGIC_VECTOR(3 downto 0);

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (a => a,
              b => b,
              s => s);

  -- Instantiation of Model Under Test.
  IC74381_0 : entity work.IC74381
    port map (a => a,
              b => b,
              s => s,
              f => f);
end tbGeneratedCode;

 

Screenshot of the Simulation in ModelSim:

 

wave_IC74381

 

Please remember this code is written in 4bits width. And I show the results in HEX!!!

 

For educational purposes I also include the netlist view of my program:

 

netlistview_IC74381