28-12-07

Running Counter on SPARTAN3E Starter Board by use of LabVIEW FPGA

Ok, I just created a next example for the Spartan3E starter board. It is a running binary counter that I send to the LED's.

 Screenshots:

countercontrol

 

counterblock
Just try to rebuild it; if you are not able to rebuild I am willing to send my bitfile to you.

 

Happy LabVIEW FPGA coding!

13-06-07

VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )

 

-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
 port(
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
  );
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

begin
output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;

 

Here is the code for a simple testbench:

 

-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;

 

I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.

 

I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:

 

even_detector

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