09-04-07

Design example for ACTEL fpga's with ARM Cortex-M1

Link: http://www.electronicstalk.com/news/ank/ank280.html

 

Synplicity and ARM have signed a joint marketing and collaboration agreement that includes a reference methodology for the recently launched ARM Cortex-M1 processor - the first ARM processor specifically designed for implementation on FPGAs.

09:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, arm, fpga, reference design, cortex-m1, softcore, processor, synplicity |  Facebook |

21-03-07

Success with IMEC and Synplicity's Synplify® Premier Software

 
 

 


Success with IMEC and Synplicity's Synplify® Premier Software
Click here to learn more about the Synplify Premier tool.

 
IMEC, a European nanoelectronics research institution, used Synplify Premier software from Synplicity to demonstrate that its C-programmable reconfigurable processor architecture ADRES is feasible for use in portable wireless multimedia devices. The entire processor system was successfully prototyped for a multimedia ADRES processor instance on a Xilinx Virtex-4 FPGA through use of the Synplify Premier tool. The Synplify Premier product provided excellent support for achieving the required clock frequency. IMEC credits the Synplify Premier tool's built-in knowledge of the FPGA's physical characteristics for the accurate timing results that it delivers. The ADRES prototype system has been important for IMEC in showing that the ADRES processor architectural template and its corresponding C-compiler are sufficiently stable for use in portable devices. 
 
 
IMEC's ADRES Innovation Promises a New Future for Hand-held Multimedia Devices
 
IMEC of Leuven, Belgium is one of the world's leading independent research institutions in nanoelectronics and nanotechnology. Its research focuses on next generation chips and systems, and bridges the gap between university research and technology development in industry. IMEC's blend of know-how and corporate relationships position the organization to help shape key technologies for future systems. 
 
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) contains two views which are tightly coupled: an array of processing elements that runs the data flow part of the application and a VLIW that executes the control. For hand-held multimedia devices, this technology delivers enormous flexibility benefits over fixed ASICs because various video codec standards can be quickly and easily accommodated through C programming. In addition, ADRES-based processors offer power efficiencies six to twelve times higher than state-of-the-art C-programmed processors. 
 
With the demonstration IMEC has proven that processors based on the ADRES architecture can deliver sufficient performance. The multimedia ADRES processor instance was developed to support MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. The demonstration employed the HAPS-32 from HARDI Electronics, which contains two Xilinx Virtex-4 LX200 FPGAs, as its prototyping board. IMEC constrained the FPGA clock input to 50 MHz to decode 30 frames/sec of H.264/AVC content at CIF resolution. 
 
Synplify Premier Tool Delivers the Necessary Performance 
 
IMEC began by synthesizing the design using the Synplify Pro product from Synplicity, the tool that had served the organization well for many years. Synplify Pro software came close to the goal at 46 MHz, but not close enough. 
 
"It was essential that we find a way to reach 50 MHz, and so we performed an investigation of the state of the art in FPGA synthesis," said Maryse Wouters, Activity Leader of the Integration Team. "Fortunately we found our answer, the Synplify Premier solution, which is capable of delivering the performance we needed. In fact it did even better than we had hoped, 52.6 MHz. Everyone was pleased with the performance gain."
 
"The reason why the Synplify Premier tool does the job better is that it understands the physical characteristics of the FPGA in fine detail and uses that knowledge to craft an optimal design," explained Wouters. "That's particularly important with the most advanced FPGAs on the market." 
 
Building on Synplify Pro technology, the Synplify Premier solution embodies its knowledge of an FPGA's specifics through a patented Synplicity technique called graph-based physical synthesis, which represents an FPGA's pre-existing wires, switches, and placement sites as a detailed routing resource graph. Graph-based physical synthesis produces rapid timing closure by automatically outputting timing-correlated legal placement and by considering availability of actual FPGA routing resources when measuring delays, rather than just physical proximity of instances. Unlike ASICs, in an FPGA physical proximity does not always correlate to timing delays, making ASIC-style physical synthesis approaches inaccurate when applied to FPGAs. Only graph-based physical synthesis can accurately estimate timing delays when performing physical synthesis.   
 
Graph-based physical synthesis also cut place-and-route runtimes significantly for IMEC. The total elapsed time for placement and routing was six hours with the Synplify Premier solution versus seventeen hours with the Synplify Pro tool. The reason is that in addition to performing synthesis, the Synplify Premier product actually places the design in a manner known to meet timing, and delivers a design that will be fully routable using the Xilinx ISE toolset. 
 
The correlation between the Synplify Premier solution's performance predictions and actuals was much better than IMEC had seen. The new tool predicted 51 MHz performance, which was very close to the actual result of 52.6 MHz.
 
IMEC's New Standard for Synthesizing 90 nm FPGAs and Below
 
With its flexibility to incorporate multiple video codec standards, the short time-to-market made possible by its high level language programmability, and its power efficiency, ADRES promises to play a major role in the next generation of mobile multimedia platforms. 
 
"Using an FPGA-based prototype platform, IMEC has demonstrated its C-programmable multimedia ADRES processor instance for real time H.264/AVC video decoding," said Wouters. "The performance gain that the Synplify Premier solution delivered was as promised in the Synplify Premier data sheet." 
 
Because of the excellent results it delivers, the Synplify Premier product has now become part of the tool flow at IMEC for future projects using leading edge FPGAs. "It is clear that for 90 nm FPGAs and beyond, the timing closure offered by the Synplify Premier tool is crucial," Wouters concluded. 
 
Click here to learn more about the Synplify Premier tool.

19-03-07

 

Actel and ARM Develop High-Performance 32-Bit Processor Optimized for FPGAs

Actel Offers New Cortex-M1 for Use in Flash-based M1 ProASIC3 and M1 Fusion Devices

MOUNTAIN VIEW, Calif., March 19, 2007 — Disclosing further details of its industry-standard processor portfolio, Actel Corporation (NASDAQ: ACTL) today announced the availability of its implementation of the ARM® Cortex™-M1 processor, a small, high-performance, 32-bit soft core co-developed by the companies for optimal use in field-programmable gate arrays (FPGAs). Removing the license and royalty fees typically associated with licensing models for industry-leading processor cores, Actel offers free access to advanced ARM processor technology to the broad marketplace. The free delivery of the Cortex-M1 processor for use in Actel's flash-based, M1-enabled Actel Fusion and ProASIC3 FPGAs provides system designers programmable flexibility and system-level integration, enabling the development of low-cost, high-performance systems.

"With the significant increase in the use of FPGAs as flexible, cost-effective platforms for the rapid design of high-quality embedded systems, the introduction of an FPGA-optimized ARM processor enables us to serve the growing needs of companies who require highly programmable solutions," said John Cornish, vice president, marketing, Processors Division, ARM. "The unprecedented security benefits and advanced features offered by Actel's flash-based FPGAs make these devices an ideal vehicle for our high-performance processor technology."

Rich Brossart, vice president, product marketing at Actel, added, "Evidenced by the success of our soft ARM7™ family processor core, designers continue to show great interest in implementing industry-standard 32-bit processor technologies in FPGAs. With the addition of the FPGA-optimized ARM Cortex-M1 processor, free of license and royalty fees, to our broad processor portfolio, system designers can select the solution that best meets their design requirements regardless of application or volume."

Cortex-M1 Processor and Actel's M1-Enabled FPGAs

Derived from ARM's three-stage Cortex-M3 processor pipeline, the highly configurable Cortex-M1 processor operates at up to 72 MHz in Actel's M1-enabled Fusion Programmable System Chip (PSC) or ProASIC3 FPGAs. Providing a good balance between size and speed for embedded applications, the core is able to be implemented in as few as 4300 tiles, roughly 20 percent of an M1A3P1000 ProASIC3 device or 30 percent of a mixed-signal M1AFS600 Actel Fusion PSC. The Cortex-M1 processor solution also connects to the industry-standard AHB bus, allowing designers to build a subsystem and easily add peripheral functionality to the processor.

With the increasing costs of application-specific integrated circuit (ASIC) design, designers can benefit from a Cortex-M1 processor-based implementation in an FPGA due to reduced design time and a lower cost of entry into system-on-chip design, particularly for lower volume applications. However, for designs that scale to ultra-high volumes, the 32-bit Cortex-M1 processor runs the industry-standard Thumb® instruction set and is upward compatible with the Cortex-M3 processor, providing an easy migration path to ASIC implementation.

Actel's flash-based FPGAs, the mixed-signal M1 Actel Fusion PSCs and low-cost M1 ProASIC3 devices, are virtually immune to tampering, assuring users that valuable IP will not be compromised or copied. The single-chip devices also provide the low power, firm-error immunity and live at power-up capabilities that are inherent to all Actel FPGAs.

Comprehensive Tool Support

The Cortex-M1 processor is supported by the comprehensive tools and knowledge that currently exists for the ARM architecture, far surpassing the level of support offered for proprietary processors. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment, and Actel Libero Integrated Design Environment—all available for free download from Actel's Web site. Actel's implementation of the Cortex-M1 processor is fully supported by the ARM RealView® Development Suite and RealView Microcontroller Development Kit. Third-party vendors, such as Aldec, CriticalBlue, CodeSourcery, IAR, ImpulseC and Keil™, an ARM Company, will also support the new processor with a host of tools—from compilers and debuggers to RTOS support.

Pricing and Availability

Actel's implementation of the Cortex-M1 processor will be available for early access in April. The M1A3P1000 ProASIC3 device and M1AFS600 Fusion PSC device will sample in Q3 2007 with production quantities in Q4 2007. Pricing for the M1 devices starts at $3.95. For further information about pricing and availability, please contact Actel or visit the company's Web site at www.actel.com .

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).

21:50 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, arm, 32-bit, softcore, core, ip, processor, actel, cortex-m1 |  Facebook |