24-02-09

Implementing RTOS (xilkernel) on Xilinx Spartan 3E Starter board

I have just published an tutorial on howto implement the xilkernel (sometimes called XMK) v4.0 on the Xilinx Spartan 3E Starter board. This xilkernel is a Real-Time Operating System (RTOS)

 

 

have fun...

 

you can also find an Round Robin Application in the rar files that is included with the tutorial...

 

http://pwo.fpga.be/RTOS/

13:53 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (3) | Tags: rtos, microblaze, fpga, softcore, xilinx, 32-bit, spartan 3e, spartantan |  Facebook |

11-09-08

1-wire LabVIEW FPGA driver

Today I posted my 1-wire driver on the NI forum. This 1-wire driver is designed to be used on a LabVIEW FPGA hardware target.

 

I developed it on the Xilinx Spartan3E board that I may use since I am a university user.

 

I try to write a lab for using this driver and also a small article in the next few days to get some more exposure in the world of LabVIEW FPGA for Xilinx board because in the future I maybe want to become a consultant in this area.

 

 

http://decibel.ni.com/content/docs/DOC-2196

11:56 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (1) | Tags: 1-wire, onewire, fpga, labview, spartan3e, ds2432, ds18s20, maxim, dallas, sha |  Facebook |

08-04-08

XIOS Hogeschool Limburg uses LabVIEW and LabVIEW FPGA to teach FPGA Applications class

Link: http://zone.ni.com/devzone/cda/tut/p/id/7154

 

More information: http://pwo.fpga.be/

 

 

 

09:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: labview fpga, fpga, classroom, digital electronics, xilinx |  Facebook |

05-03-08

7-segment Display on Xilinx SPARTAN3E Starter board with LabVIEW FPGA

This Application show an LabVIEW VI that is working as a driver for a 7-segment display.

project weblink:
http://decibel.ni.com/content/docs/DOC-1407;jsessionid=82a40f1930d9ca4239899c184ad6a899bef577ef252d.e38MaNyPaNePaO0Lch8Lax8Kc38Le6fznA5Pp7e

code weblink:
http://decibel.ni.com/content/servlet/JiveServlet/download/1407-2-1586/FPGA%20VI%207%20SEGMENT.zip

Requirements: Application Software: LabVIEW Professional Development System 8.5 Addon Software: LabVIEW FPGA Module 8.5

I developed this Application on my Xilinx SPARTAN3E Starter Board. I used a Kingbright SA52-11 7-segment display.

Enjoy

29-12-07

FPGA Mindmap

I just started to create my own FPGA Mindmap; if you would like to contribute just contact me! 

 

 

15:16 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: mindmap, fpga, contribute, technology |  Facebook |

28-12-07

Running Counter on SPARTAN3E Starter Board by use of LabVIEW FPGA

Ok, I just created a next example for the Spartan3E starter board. It is a running binary counter that I send to the LED's.

 Screenshots:

countercontrol

 

counterblock
Just try to rebuild it; if you are not able to rebuild I am willing to send my bitfile to you.

 

Happy LabVIEW FPGA coding!

18-12-07

ESL with LabVIEW FPGA

Today I experimented with LabVIEW FPGA targetting the Spartan3E University board. I worked all the projects out that where included in the pdf file you can get on the academic website of NI (National Instruments - http://www.ni.com ).

I have made:

* the LED example

* the LCD example

* the Switch example where you start from a empty project

* including an Xilinx ISE generated FIR filter (IP core integrating into LabVIEW FPGA) with this example I had some problems because the value of the signal that I sended to the ADC was not the correct value that was shown on my PC screen.

 

Links that could be handy:

* Spartan3E user guide of the starter board:

http://www.xilinx.com/support/documentation/boards_and_ki...

* download Spartan3E LabVIEW FPGA driver

http://digital.ni.com/express.nsf/bycode/spartan3e

* WORD version of the LabVIEW FPGA tutorial for the Spartan3E starter university board (for easy copy/pasting of the VHDL code for the IP core that has to be implemented :-) )

http://etidweb.tamu.edu/ftp/ENTC219/LabView/Getting%20Sta...

enjoy!

20-11-07

FPGA from Scratch

Just found a good blog for anyone starting with Xilinx FPGA's (EDK,...)

 

check out:

http://svenand.blogdrive.com/archive/40.html

 

enjoy!

16:26 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, edk, scratch, start, xilinx |  Facebook |

10-11-07

Advanced Tools in Reconfigurable Computing

I just found and interesting post on a blog on Reconfigurable Computing that I would like to share with you (visitors of this blog).

The future of FPGA programming will be C-based. You program the hardware in C (systemC, handel-C,...) and the software in C (HW/SW codesign).

 

enjoy reading

 

here is the link:

http://asic-soc.blogspot.com/2007/11/advanced-tools-in-re...

14:25 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: reconfigurable, tools, hw sw codesign, fpga, computing, handel-c, systemc |  Facebook |

04-11-07

Cracking GSM with SDR

I just found an article on howto beat the security of GSM. Read the story and watch the video on howto crack the GSM security with a Software Defined Radio. This technology let you listen and see every voice/sms on the GSM network.

 

http://swik.net/User:stinkyworld/hackszine/Decrypting+GSM...

 

09:07 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: gsm, sdr, fpga, gnuradio, crack, a5 1 |  Facebook |

21-10-07

Nice Hobby Electronic projects for the weekends ;-)

I just found 2 nice projects for everyone related to software or hardware projects:

 

http://wiki.openbeacon.org/wiki/OpenBeacon_USB

http://www.openbeacon.org/ --> RfID receiver !!!

 

http://lekernel.lya.eu/ula.html --> Logic Analyzer USB2.0 and FPGA based!

 

Check them out dudes, they are really cool!

 

 

 

12:12 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: usb, vhdl, fpga, rfid |  Facebook |

03-10-07

VHDL Project for LCD

I just found the next interesting article on controlling an LCD from an FPGA board by use of VHDL check out this link:

 

http://www.xess.com/projects/LCD_HD44780.pdf

design files: http://www.xess.com/projects/LCD_HD44780.ZIP

 

enjoy ;-)

17:06 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: vhdl, lcd, example, fpga, article |  Facebook |

29-08-07

Soon Actel FPGA's for the mass!!!

Today I have read the following article: http://www.pldesignline.com/201802670?cid=RSSfeed_program...

This looks like a nice module; especially for solution providers that don't make their own boards. This board is also a nice tool to use in the education sector like in the Universities. 

 

I am convinced that for learning purposes of FPGA programming it is better to start with the design flow for ACTEL fpga's. Every step you make is clear in their Libero IDE toolchain.

 

I hope that the price will soon fall down of that module so that their is an change to create a more community of ACTEL FPGA Developers.

 

09:47 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: fpga, actel, module, proasic3, community |  Facebook |

20-08-07

Install Linux on H3650 IPAQ

Today I am trying to install familiar linux on my IPAQ H3850 to have a handheld computer to write some regular software on to communicate with some of my ACTEL FPGA boards. More information will follow.

 

More information on: http://www.handhelds.org

 

 

 

 

17:04 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, linux |  Facebook |

16-08-07

CoreABC - Binary Counter

Another example of the binary counter implemented as a SoC on an ACTEL ProASIC3 FPGA by use of the CoreABC and CoreGPIO softcore microprocessor.

 Enjoy this educational example.

// http://mobile.skynetblogs.be

// Vincent Claes 

LOAD 1
$Main
APBWRT ACC 0 0
CALL $Wait500ms
ADD 1
APBWRT ACC 0 0
CALL $Wait500ms
JUMP $Main

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

 

12:14 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, coregpio, soc |  Facebook |

15-08-07

Another Example for CoreABC Programming on the ACTEL FPGA

Here is the code; I don't have many time at this moment so there is no information included :-) If you need some just reply to this post and I will explain the code.

 This program shows you a running led (only one time) everytime you enable the processor


$LedOff    IOWRT ACC
    CALL $Wait500ms
$LedOn    SHL0
    CALL $Wait500ms
    JUMP $LedOff

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

10:24 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: coreabc, fpga, actel |  Facebook |

19-06-07

Libero v8.0

I have just downloaded my copy of Libero Version 8.0. I have just started it for seeing the UI. The SmartDesign tool in the Libero IDE will be easy to use I think. Soon I will post here a small example on how to use it... I have other work to do at this time sorry guys ;-)

 

For the release notes see the following link: http://www.actel.com/download/software/libero/libero80rl....

 

 

A Project manager in Libero IDE whoohw!!!

 

SmartDesign will be amazing!

11:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: smartdesign, libero, actel, fpga, esl |  Facebook |

14-06-07

VHDL code for an 74-series ALU (the 74LS381 chip)

Hereby I give you my code of the 74LS381 IC, which is an ALU with 4-bits width.

 

The VHDL Code:

-- IC74381.vhd
-- Developed by Vincent Claes
-- claesvincent (at) gmail.com

-- http://mobile.skynetblogs.be
-- 2007 (c)
--
-- This version is a simlified version of the 74LS381 IC. It shows the main functionality in VHDL
-- It is developed for educational purposes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  s2  s1  s0  operation
--------------------------
--  L   L   L   clear
--  L   L   H   B minus A
--  L   H   L   A minus B
--  L   H   H   A plus B
--  H   L   L   A xor B
--  H   L   H   A + B
--  H   H   L   AB
--  H   H   H   PRESET  

entity IC74381 is
port(   a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        s: in std_logic_vector (2 downto 0);
        f: out std_logic_vector (3 downto 0)
);
end IC74381;

architecture arch of IC74381 is
signal BminusA,AminusB,AplusB,AxorB,AandB,AB: std_logic_vector(3 downto 0);
signal au,bv0,bv1,bv2,bv3: unsigned(3 downto 0);
signal p0,p1,p2,p3,prod: unsigned(7 downto 0);

begin

BminusA <=  std_logic_vector(signed(b)-signed(a));
AminusB <=  std_logic_vector(signed(a)-signed(b));
AplusB  <=  std_logic_vector(signed(a)+signed(b));
AxorB   <= a xor b;
AandB   <= a and b;

au  <=unsigned(a);
bv0 <=(others=>b(0));
bv1 <=(others=>b(1));
bv2 <=(others=>b(2));
bv3 <=(others=>b(3));
p0  <="0000" & (bv0 and au);
p1  <="000"&(bv1 and au) & "0";
p2  <="00" & (bv2 and au) & "00";
p3  <="0" & (bv3 and au) & "000";
prod<=((p0+p1)+(p2+p3));
AB<=std_logic_vector(prod(3 downto 0));

f   <=  "0000"      when s="000" else
        BminusA     when s="001" else
        AminusB     when s="010" else
        AplusB      when s="011" else
        AxorB       when s="100" else
        AandB       when s="101" else
        AB          when s="110" else
        "1111"; 
end arch;

 

 

The testbench code:

 

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    a : inout std_logic_vector(3 downto 0) := x"7";
    b : inout std_logic_vector(3 downto 0) := x"3";
    s : inout std_logic_vector(2 downto 0));

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 10 ns;
    s <= "101";
    wait for 10 ns;
    s <= "110";
    wait for 10 ns;
    s <= "111";
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 20 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal a : std_logic_vector(3 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal s : std_logic_vector(2 downto 0);
  signal f : STD_LOGIC_VECTOR(3 downto 0);

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (a => a,
              b => b,
              s => s);

  -- Instantiation of Model Under Test.
  IC74381_0 : entity work.IC74381
    port map (a => a,
              b => b,
              s => s,
              f => f);
end tbGeneratedCode;

 

Screenshot of the Simulation in ModelSim:

 

wave_IC74381

 

Please remember this code is written in 4bits width. And I show the results in HEX!!!

 

For educational purposes I also include the netlist view of my program:

 

netlistview_IC74381

 

13-06-07

VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )

 

-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
 port(
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
  );
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

begin
output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;

 

Here is the code for a simple testbench:

 

-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;

 

I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.

 

I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:

 

even_detector

13:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: synplify, fpga, libero ide, example, modelsim, vhdl, hardware, programming, actel, actl |  Facebook |

27-05-07

Interesting Links for (Open Source) Software defined radio (SDR)

I have found some interesting articles on SDR (software defined radio)

 

check them out:

 

http://www.tapr.org/

http://www.gnu.org/software/gnuradio/

http://www.amqrp.org/kits/softrock40/

http://www.arrl.org/tis/info/sdr.html

http://hpsdr.org/ (High Performance Software Defined Radio)

http://www.brudirect.com/DailyInfo/News/Archive/May07/260...

 

Enjoy the links!

12-05-07

How to choose the right RTOS

Since today we all want to install an OS on an FPGA let's have a look at a nice article on Programmable Logic Deisgnline:

 

link: http://www.pldesignline.com/howto/showArticle.jhtml?artic...

 

This article helps you with making a choose for a RTOS for your FPGA/ASIC platform.

11:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: asic, platform, rtos, fpga |  Facebook |

30-04-07

Open Source Soft Microprocessors

I found a nice article on Opensource Soft Microprocessors.

 

here is the link:

 

http://www.byte.com/documents/s=10114/byt1173555136952/

 

16:26 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: opensource, softcore, microprocessor, fpga |  Facebook |

25-04-07

Actel Announces First Quarter 2007 Revenues Options

Mountain View, Calif. -- Apr 24, 2007 --  Actel Corporation (NASDAQ:
ACTL) today announced net revenues for the first quarter of 2007,
which ended April 1, 2007. No additional financial results for the
first quarter will be available until after completion of the ongoing
review of the Company's historical stock option practices and related
accounting.

Net revenues for the first quarter of 2007 were $48.6 million, up 5
percent from the first quarter of 2006 and up one percent from the
fourth quarter of 2006.

Revenue Outlook - Second Quarter 2007

The Company believes that second quarter revenues will be flat
sequentially, plus or minus two percent. This is a "forward-looking
statement" within the meaning of the Private Securities Litigation
Reform Act of 1995 and should be read with the "Risk Factors" in the
Company's most recent Form 10-Q, which can be found on Actel's web
site, www.actel.com. The Company's quarterly revenues are subject to a
multitude of risks, including general economic conditions and a
variety of risks specific to Actel or characteristic of the
semiconductor industry, such as fluctuating demand, intense
competition, rapid technological change and related intellectual
property and international trade issues, wafer and other supply
shortages, and booking and shipment uncertainties. These and the other
Risk Factors make it difficult for the Company to accurately project
quarterly revenues, and could cause actual results to differ
materially from those projected in the forward-looking statement.
Actel does not assume, and expressly disclaims, any duty to update the
forward-looking statement and Risk Factors.

Stock Option Review

As previously announced:

On September 22, 2006, a Special Committee of the Board of Directors
of Actel, composed of independent directors and assisted by
independent counsel, was appointed to review the Company's historical
stock option grant practices and related accounting.
Actel voluntarily informed the staff of the Securities and Exchange
Commission ("SEC") about the internal review and is cooperating with
the SEC in its informal inquiry.
On January 18, 2007, Actel's management concluded that shareholders
and other investors should no longer rely on the Company's financial
statements and the related reports or interim reviews of Actel's
independent registered public accounting firm and all earnings press
releases and similar communications issued by the Company for fiscal
periods commencing on or after January 1, 1996.
On January 30, 2007, the Special Committee presented its preliminary
findings to the Board of Directors. The preliminary findings are
described in a Current Report on Form 8-K filed by Actel on February
1, 2007.
On March 9, 2007, the Special Committee delivered its final report to
the Board of Directors.
Working with its independent registered public accounting firm, the
Company is evaluating corrections to measurement dates and other
related accounting issues and is quantifying the financial and tax
impact of those corrections and related issues. In lieu of amending
its prior SEC filings to restate financial statements, Actel intends
to include in its Annual Report on Form 10-K for the fiscal year ended
December 31, 2006, the comprehensive disclosure outlined in guidance
posted by the SEC Chief Accountant's Office on January 16, 2007.
The Company has received notices from The Nasdaq Stock Market
("Nasdaq") of staff determinations that Actel is not in compliance
with the requirement for continued listing set forth in Nasdaq
Marketplace Rule 4310(c)(14), under which listed companies must file
all required SEC reports, and Rules 4350(e) and 4350(g), under which
companies must hold an annual meeting of shareholders, solicit
proxies, and provide proxy statements to Nasdaq. On February 16, 2007,
a Nasdaq Listing Qualifications Panel ("Panel") granted the Company's
request for continued listing, subject to certain conditions.
On April 2, 2007, the Nasdaq Listing and Hearing Review Council
("Listing Council") stayed the February 16, 2007, decision of the
Panel pending a review by the Listing Council of the merits of the
Panel's decision. By June 20, 2007, the Nasdaq Listing Qualifications
Department will provide the Listing Council with an updated
qualifications summary sheet and any additional information that staff
believes would assist the Listing Council in its review of this
matter. The Company may submit any additional information that it
wishes the Listing Council to consider by June 29, 2007.

The Company will not announce full financial results for the first
quarter of 2007 until it files its Quarterly Report on Form 10-Q for
the fiscal quarter ended April 1, 2007. The Company intends to file
its delinquent SEC periodic reports, including any required
restatements, and solicit proxies and hold an annual shareholders'
meeting as soon as practicable.

21:14 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: 2007, actl, california, actel, revenues, mountain view, fpga |  Facebook |

22-04-07

Binary Coded Decimal (BCD) with FPGA's

On pldesignline there is an article on BCD code on FPGA's, a must read for all people who work with FPGA's.

 

 

Link:

http://www.pldesignline.com/howto/199001229

 

11:45 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: bcd, fpga, pld |  Facebook |

09-04-07

Design example for ACTEL fpga's with ARM Cortex-M1

Link: http://www.electronicstalk.com/news/ank/ank280.html

 

Synplicity and ARM have signed a joint marketing and collaboration agreement that includes a reference methodology for the recently launched ARM Cortex-M1 processor - the first ARM processor specifically designed for implementation on FPGAs.

09:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, arm, fpga, reference design, cortex-m1, softcore, processor, synplicity |  Facebook |

21-03-07

Success with IMEC and Synplicity's Synplify® Premier Software

 
 

 


Success with IMEC and Synplicity's Synplify® Premier Software
Click here to learn more about the Synplify Premier tool.

 
IMEC, a European nanoelectronics research institution, used Synplify Premier software from Synplicity to demonstrate that its C-programmable reconfigurable processor architecture ADRES is feasible for use in portable wireless multimedia devices. The entire processor system was successfully prototyped for a multimedia ADRES processor instance on a Xilinx Virtex-4 FPGA through use of the Synplify Premier tool. The Synplify Premier product provided excellent support for achieving the required clock frequency. IMEC credits the Synplify Premier tool's built-in knowledge of the FPGA's physical characteristics for the accurate timing results that it delivers. The ADRES prototype system has been important for IMEC in showing that the ADRES processor architectural template and its corresponding C-compiler are sufficiently stable for use in portable devices. 
 
 
IMEC's ADRES Innovation Promises a New Future for Hand-held Multimedia Devices
 
IMEC of Leuven, Belgium is one of the world's leading independent research institutions in nanoelectronics and nanotechnology. Its research focuses on next generation chips and systems, and bridges the gap between university research and technology development in industry. IMEC's blend of know-how and corporate relationships position the organization to help shape key technologies for future systems. 
 
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) contains two views which are tightly coupled: an array of processing elements that runs the data flow part of the application and a VLIW that executes the control. For hand-held multimedia devices, this technology delivers enormous flexibility benefits over fixed ASICs because various video codec standards can be quickly and easily accommodated through C programming. In addition, ADRES-based processors offer power efficiencies six to twelve times higher than state-of-the-art C-programmed processors. 
 
With the demonstration IMEC has proven that processors based on the ADRES architecture can deliver sufficient performance. The multimedia ADRES processor instance was developed to support MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. The demonstration employed the HAPS-32 from HARDI Electronics, which contains two Xilinx Virtex-4 LX200 FPGAs, as its prototyping board. IMEC constrained the FPGA clock input to 50 MHz to decode 30 frames/sec of H.264/AVC content at CIF resolution. 
 
Synplify Premier Tool Delivers the Necessary Performance 
 
IMEC began by synthesizing the design using the Synplify Pro product from Synplicity, the tool that had served the organization well for many years. Synplify Pro software came close to the goal at 46 MHz, but not close enough. 
 
"It was essential that we find a way to reach 50 MHz, and so we performed an investigation of the state of the art in FPGA synthesis," said Maryse Wouters, Activity Leader of the Integration Team. "Fortunately we found our answer, the Synplify Premier solution, which is capable of delivering the performance we needed. In fact it did even better than we had hoped, 52.6 MHz. Everyone was pleased with the performance gain."
 
"The reason why the Synplify Premier tool does the job better is that it understands the physical characteristics of the FPGA in fine detail and uses that knowledge to craft an optimal design," explained Wouters. "That's particularly important with the most advanced FPGAs on the market." 
 
Building on Synplify Pro technology, the Synplify Premier solution embodies its knowledge of an FPGA's specifics through a patented Synplicity technique called graph-based physical synthesis, which represents an FPGA's pre-existing wires, switches, and placement sites as a detailed routing resource graph. Graph-based physical synthesis produces rapid timing closure by automatically outputting timing-correlated legal placement and by considering availability of actual FPGA routing resources when measuring delays, rather than just physical proximity of instances. Unlike ASICs, in an FPGA physical proximity does not always correlate to timing delays, making ASIC-style physical synthesis approaches inaccurate when applied to FPGAs. Only graph-based physical synthesis can accurately estimate timing delays when performing physical synthesis.   
 
Graph-based physical synthesis also cut place-and-route runtimes significantly for IMEC. The total elapsed time for placement and routing was six hours with the Synplify Premier solution versus seventeen hours with the Synplify Pro tool. The reason is that in addition to performing synthesis, the Synplify Premier product actually places the design in a manner known to meet timing, and delivers a design that will be fully routable using the Xilinx ISE toolset. 
 
The correlation between the Synplify Premier solution's performance predictions and actuals was much better than IMEC had seen. The new tool predicted 51 MHz performance, which was very close to the actual result of 52.6 MHz.
 
IMEC's New Standard for Synthesizing 90 nm FPGAs and Below
 
With its flexibility to incorporate multiple video codec standards, the short time-to-market made possible by its high level language programmability, and its power efficiency, ADRES promises to play a major role in the next generation of mobile multimedia platforms. 
 
"Using an FPGA-based prototype platform, IMEC has demonstrated its C-programmable multimedia ADRES processor instance for real time H.264/AVC video decoding," said Wouters. "The performance gain that the Synplify Premier solution delivered was as promised in the Synplify Premier data sheet." 
 
Because of the excellent results it delivers, the Synplify Premier product has now become part of the tool flow at IMEC for future projects using leading edge FPGAs. "It is clear that for 90 nm FPGAs and beyond, the timing closure offered by the Synplify Premier tool is crucial," Wouters concluded. 
 
Click here to learn more about the Synplify Premier tool.

19-03-07

Thursday 22/03/2007: "Analog meets Digital on snow" seminar

Thursday there is a ACAL (ACTEL representative for Belgium) seminar planned. Here are the topics that will be handled:

 

Agenda :
        08:30 - 09:00 : Registration + Breakfast
        09:00 - 09:05 : Welcome (Guy Maertens MD Acal Belgium)
        09:05 - 11:00 : Power (Jens Hedrich FAE Linear Technology)
        11:00 - 11:15 : Coffee Break
        11:15 - 12:00 : Data Conversion (Jens Hedrich FAE Linear Technology)
        12:00 - 13:00 : Bruegelian Buffet
        13:00 - 13:15 : Igloo Launch (Vaughan Price Managing Director Actel Europe)
        13:15 - 13:45 : New Technology Solutions (Patrizio Piasentin Regional Sales Manager Actel)
        13:45 - 14:30 : System Management, µTCA, MotorControl (Luca Cattaneo ETM Actel)
        14:30 - 14:45 : Coffee Break
        14:45 - 15:30 : Low Power Design Tricks (Luca Cattaneo ETM Actel)
        16:00 - 18:00 : Ski & Snowboard Session + Snacks
        18:15 - 19:00 : Appetizers and Prize Giving

 

More information can be found here:

http://www.acal.be/index.php?module=calendar&calendar...

22:01 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: acal, actel, snow, fpga, actel europe |  Facebook |

 

Actel and ARM Develop High-Performance 32-Bit Processor Optimized for FPGAs

Actel Offers New Cortex-M1 for Use in Flash-based M1 ProASIC3 and M1 Fusion Devices

MOUNTAIN VIEW, Calif., March 19, 2007 — Disclosing further details of its industry-standard processor portfolio, Actel Corporation (NASDAQ: ACTL) today announced the availability of its implementation of the ARM® Cortex™-M1 processor, a small, high-performance, 32-bit soft core co-developed by the companies for optimal use in field-programmable gate arrays (FPGAs). Removing the license and royalty fees typically associated with licensing models for industry-leading processor cores, Actel offers free access to advanced ARM processor technology to the broad marketplace. The free delivery of the Cortex-M1 processor for use in Actel's flash-based, M1-enabled Actel Fusion and ProASIC3 FPGAs provides system designers programmable flexibility and system-level integration, enabling the development of low-cost, high-performance systems.

"With the significant increase in the use of FPGAs as flexible, cost-effective platforms for the rapid design of high-quality embedded systems, the introduction of an FPGA-optimized ARM processor enables us to serve the growing needs of companies who require highly programmable solutions," said John Cornish, vice president, marketing, Processors Division, ARM. "The unprecedented security benefits and advanced features offered by Actel's flash-based FPGAs make these devices an ideal vehicle for our high-performance processor technology."

Rich Brossart, vice president, product marketing at Actel, added, "Evidenced by the success of our soft ARM7™ family processor core, designers continue to show great interest in implementing industry-standard 32-bit processor technologies in FPGAs. With the addition of the FPGA-optimized ARM Cortex-M1 processor, free of license and royalty fees, to our broad processor portfolio, system designers can select the solution that best meets their design requirements regardless of application or volume."

Cortex-M1 Processor and Actel's M1-Enabled FPGAs

Derived from ARM's three-stage Cortex-M3 processor pipeline, the highly configurable Cortex-M1 processor operates at up to 72 MHz in Actel's M1-enabled Fusion Programmable System Chip (PSC) or ProASIC3 FPGAs. Providing a good balance between size and speed for embedded applications, the core is able to be implemented in as few as 4300 tiles, roughly 20 percent of an M1A3P1000 ProASIC3 device or 30 percent of a mixed-signal M1AFS600 Actel Fusion PSC. The Cortex-M1 processor solution also connects to the industry-standard AHB bus, allowing designers to build a subsystem and easily add peripheral functionality to the processor.

With the increasing costs of application-specific integrated circuit (ASIC) design, designers can benefit from a Cortex-M1 processor-based implementation in an FPGA due to reduced design time and a lower cost of entry into system-on-chip design, particularly for lower volume applications. However, for designs that scale to ultra-high volumes, the 32-bit Cortex-M1 processor runs the industry-standard Thumb® instruction set and is upward compatible with the Cortex-M3 processor, providing an easy migration path to ASIC implementation.

Actel's flash-based FPGAs, the mixed-signal M1 Actel Fusion PSCs and low-cost M1 ProASIC3 devices, are virtually immune to tampering, assuring users that valuable IP will not be compromised or copied. The single-chip devices also provide the low power, firm-error immunity and live at power-up capabilities that are inherent to all Actel FPGAs.

Comprehensive Tool Support

The Cortex-M1 processor is supported by the comprehensive tools and knowledge that currently exists for the ARM architecture, far surpassing the level of support offered for proprietary processors. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment, and Actel Libero Integrated Design Environment—all available for free download from Actel's Web site. Actel's implementation of the Cortex-M1 processor is fully supported by the ARM RealView® Development Suite and RealView Microcontroller Development Kit. Third-party vendors, such as Aldec, CriticalBlue, CodeSourcery, IAR, ImpulseC and Keil™, an ARM Company, will also support the new processor with a host of tools—from compilers and debuggers to RTOS support.

Pricing and Availability

Actel's implementation of the Cortex-M1 processor will be available for early access in April. The M1A3P1000 ProASIC3 device and M1AFS600 Fusion PSC device will sample in Q3 2007 with production quantities in Q4 2007. Pricing for the M1 devices starts at $3.95. For further information about pricing and availability, please contact Actel or visit the company's Web site at www.actel.com .

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).

21:50 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, arm, 32-bit, softcore, core, ip, processor, actel, cortex-m1 |  Facebook |

ARM Extends Cortex Family With First Processor Optimized for FPGA

ARM Extends Cortex Family With First Processor Optimized for FPGA

The ARM Cortex-M1 processor enables OEMs to reduce development costs throughstandardization on a single architecture across FPGA, ASIC and ASSP

CAMBRIDGE, UK, March 19, 2007 — ARM [(LSE:ARM); (Nasdaq: ARMHY)] today announced the availability of the ARM® Cortex™-M1 processor – the first ARM processor designed specifically for implementation on FPGAs. The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers.

ARM and Actel will both be demonstrating the Cortex-M1 processor at the Embedded Systems Conference in San Jose, Calif., April 2-5.

The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor. The Cortex-M1 processor is supported by leading FPGA synthesis vendors, software development tools, and real-time operating systems, giving FPGA designers unprecedented choice and flexibility.

"Gartner Dataquest maintains that FPGAs/PLDs have a very bright future," said Bryan Lewis, research vice president, Gartner Dataquest. "We expect solid growth (15.7 percent) to resume in 2008 and forecast the FPGA/PLD market to outperform semiconductors from 2008 onward."1
"The Cortex-M1 processor extends the reach of the ARM architecture in the FPGA domain, and advances our goal of providing processor solutions for the entire digital world," said Graham Budd, EVP and general manager, Processor Division, ARM. "By leveraging ARM's vast installed user base in the ASIC/ASSP and microcontroller markets, along with support from our own RealView® family of tools as well as product support from the ARM Connected Community, the Cortex-M1 processor will deliver significant savings to OEMs in terms of software development resources, tools, and training."

Actel has licensed the Cortex-M1 processor and will make it available at no additional cost to their customers. The FPGA-optimized Cortex-M1 processor offers users of Actel's flash-based M1-enabled Actel Fusion Programmable System Chips and ProASIC3 FPGAs a compact and efficient processor satisfying the requirements of a wide range of end applications. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment and Actel Libero Integrated Design Environment – all available for free download from Actel's website.

"Following the success of our ARM7™ family-based solutions, Actel worked closely with ARM to optimize its Cortex-M1 processor for FPGA implementation from the ground up, making it an extremely valuable addition to our growing processor library," said Rich Brossart, vice president, product marketing, Actel. "Free of the contract negotiations and fees typically associated with industry-standard processor cores, Actel will make the Cortex-M1 processor available to those companies who desire highly programmable solutions regardless of application or volume."

Tools and Peripherals Support

The Cortex-M1 processor will be fully supported by forthcoming releases of the ARM RealView® Development Suite and RealView Microcontroller Development Kit. The RealView Development Suite will include a complete instruction set system model (ISSM) allowing developers to create and test applications for the Cortex-M1 processor out of the box. Developers can easily customize the RealView Development Suite's debugger to visualize and interact withperipherals added around a Cortex-M1 processor, and will also be able to connect and debug applications running on Cortex-M1 silicon using ARM's high-performance RealView ICE and ULINK®2 run control units.

System performance and design turn around time are boosted further with ARM AMBA® compliant PrimeCell® peripheral IP, including ARM's latest ultra-efficient microDMA (PL230).
ARM Connected Community Partners, including CodeSourcery, Express Logic, IAR Systems, Mentor Graphics Inc., Micrium and Synplicity will all support the Cortex-M1 processor. For improved flow integration, the Cortex-M1 processor deliverables will include an IP description conforming to the IP-XACT standard from The SPIRIT Consortium.

Low area, high frequency and ease of use

The ARM Cortex-M1 processor is a streamlined three-stage 32-bit RISC processor that implements a subset of the popular, high density Thumb®-2 instruction set. This enables both the processor and software footprint to meet the area budget of the smallest FPGA devices, while retaining compatibility with Thumb code for any ARM processor from the ARM7TDMI® processor upwards.The Cortex-M1 processor is capable of more than 170 MHz, whilst occupying less than 15 percent area of popular low-cost FPGA devices. Despite being the smallest processor in the Cortex family, the Cortex-M1 processor can deliver 0.8 DMIPS/MHz. Typical applications for the Cortex-M1 processor on FPGAs include embedded control, communications, networking and aerospace.

More information on ARM solutions in FPGA is available from www.arm.com/fpga.

Availability

Free of license and royalty fees, Actel's implementation of the Cortex-M1 processor will be available for early access in April via the Actel website www.actel.com. The M1-enabled ProASIC3 and Actel Fusion PSC devices will sample in Q3 2007.

The ARM Cortex-M1 processor RTL and associated EDA views optimized for a range of FPGA vendor devices including Actel, Altera, Lattice and Xilinx will be available for license by OEMs in 2Q'07.

About the ARM Cortex Family of Processors

The three series in the ARM Cortex family enable chip manufacturers and OEMs to standardize around a single architecture from low-end microcontrollers to high-performance applications processors. Featuring Thumb-2 technology, the ARM Cortexfamily significantly reduces development costs and increases enterprise efficiency.

  • ARM Cortex-A Series: Applications processors for complex OS and user applications
  • ARM Cortex-R Series: Embedded processors for real-time systems
  • ARM Cortex-M Series: Deeply embedded processors optimized for microcontroller and low-cost applications

About ARM
ARM designs the technology that lies at the heart of advanced digital products, frommobile, home and enterprise solutions toembedded and emerging applications. ARM's comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphics processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.

About the ARM Connected Community
The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions. For more information, please visit http://www.arm.com/community.

ENDS

1. Gartner, Inc., "Forecast: ASIC/ASSP, FPGA/PLD and SLI/SOC Applications, Worldwide, 2002-2010 (4Q06 Update)", by John Barber and Bryan Lewis, December 4, 2006.

ARM, Thumb, RealView, PrimeCell and ARM7TDMI are registered trademarks of ARM Limited. Cortex and ARM7 are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; and ARM Physical IP, Inc.; and ARM Norway AS.

Contact: Stephanie Mrus, Actel Corporation, 650.318.4614

21:49 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, fpga, actel, cortex-m1, oem |  Facebook |

17-03-07

ACTEL FPGA developers community

I just opened the ACTEL FPGA developers community which is a mailinglist of all Actel FPGA developers. It will be a meeting place from ACTEL FPGA developers all over the world. If you would like to know where people are working on with ACTEL fpga's just join the mailinglist.

 

 

 

Bètaversie van Google Discussiegroepen
ACTEL FPGA developers
Naar deze groep gaan

 

 

 

Bètaversie van Google Discussiegroepen
Aanmelden bij ACTEL FPGA developers
E-mailadres:
Naar deze groep gaan

14:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, developers, community, fpga |  Facebook |