Arasan Chip Systems Extends USB IP Offerings to Actel’s CompanionCore Program

Source: http://www.fpgajournal.com/news_2007/03/20070306_02.htm


SAN JOSE, Calif.--(BUSINESS WIRE)--Arasan Chip Systems, Inc. (“Arasan”), a leading supplier of reusable intellectual property (IP) cores, semiconductors and design services, today announced that it has joined Actel Corporation’s CompanionCore Alliance Program. Arasan has optimized its USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores for use with Actel’s flash-based, single-chip Actel Fusion, IGLOO, ProASIC3/E and ProASIC Plus field-programmable gate arrays (FPGAs). With these USB IP offerings, system designers have access to proven building blocks to streamline design and development, shorten time to market and reduce design costs and risks.

Actel CompanionCore products offer seamless implementation through Actel's suite of internal and third-party EDA development tools, documentation, and quality service and support, thereby streamlining the design process. Specific FPGA target data is available for each IP core on the CompanionCore Web site at http://www.actel.com/products/partners/companioncore/.

“We are excited about the opportunity to partner with Actel in its CompanionCore program,” said Kevin Walsh, vice president of marketing at Arasan Chip Systems. “Our customers can confidently use these USB cores, and others that we intend to put into the program, knowing we have done all the work to optimize them for use in Actel’s FPGAs.”

Rich Brossart, Actel vice president, product marketing said, "Arasan’s USB IP solutions complement Actel's flash-based devices, including the company’s innovative Actel Fusion, IGLOO, and ProASIC3/E FPGAs. For customers requiring USB connectivity, the addition of Arasan’s USB 2.0 Host, 2.0 Hub, 2.0 Device and OTG cores to the Actel CompanionCore program will enhance designer productivity and versatility while reducing time to market."

Total Technology Solution

Arasan provides a total technology solution to all its licensees, including IP source code, a test environment, sample device drivers, synthesis scripts, and complete technical documentation. The total technology solution also includes optional product design development tools like the hardware validation platform and software targeted for Linux. Custom bus integration services are offered to integrate the IP in a customer specific manner. Available for purchase, Arasan’s validation platform is a stand-alone board used to ease compliance testing of as well as prototyping, including driver development.

Pricing and Availability

Licenses for the USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores are available from Arasan in either synthesizable RTL or Actel-targeted netlist formats. The USB cores are available under special license terms. For more information on these IP cores, please visit Arasan at http://www.arasan.com or Actel at http://www.actel.com/products/ip/.

About Arasan

Arasan Chip Systems Inc. founded in 1995, is a leading supplier of Reusable Intellectual Property (IP’s) cores, semiconductors and electronic design services. Arasan’s product portfolio is focused on Bus Interfaces and includes IP’s for USB 1.1 & 2.0, PCI, SDIO and CE-ATA technologies. Arasan’s products and services enable businesses to develop and leverage product design and development. Arasan Chip Systems has been an executive member of SD Card Association since 2001, MMCA since 2003 and CE-ATA since 2004. Arasan is headquartered in San Jose, California, with design centers in India and support options available in Taiwan, China & Europe. Licensees of Arasan’s USB IP include companies like TI, Cisco, NEC, Staccato, Los Alamos National Laboratory, and General Atomics.

Visit: www.arasan.com for more product information.


The Top-10 Programmable Logic "How To" articles of 2006

As most of the visitors of this blog are interested in FPGA and their technology I hereby put some of the most interesting articles about technology about FPGA's and everything around (or inside ) them. Enjoy this links 


#10 Alternative computing solutions, from single cores to arrays of 'things'
There are many ways of performing computations, including single CPU or DSP processors (chips or cores), multiple processors, arrays of "things", and "great big piles of gates."

#9 The state-of-play in multi-processor and reconfigurable computing
When a conventional processor (core) cannot meet the needs of a target application, it becomes necessary to evaluate alternative solutions such as multiple cores and/or configurable cores.

#8: How to take advantage of partial reconfiguration in FPGA designs.
The capability of designs to leverage partial reconfiguration opens doors to a whole host of applications.

#7: How to invert three signals with only two NOT gates (and *no* XOR gates): Part 2.
In part two of this article, we consider a dynamic solution to our original problem (using a ring oscillator and other "stuff"); also, we learn how to implement a NOT gate using four AND gates!

#6: FPGA Architectures from 'A' to 'Z' – Part 2.
If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.

#5: All About FPGAs.
An industry expert examines field-programmable gate arrays (FPGAs), including current and forthcoming architectures, technologies, and software tools.

#4: How to implement a digital oscilloscope in Structured ASIC fabric.
Structured ASICs provide quicker time-to-market and lower development costs than standard ASICs, while also providing higher performance and lower unit costs than FPGAs.

#3: How to invert three signals with only two NOT gates (and *no* XOR gates): Part 1
Even for hardened logic designers, these solutions will delight and entertain; also, there's a new "Brain Boggler" to be pondered.

#2: FPGA architectures from 'A' to 'Z' – Part 1
If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this two-part tutorial explains all.

#1: An introduction to different rounding algorithms
The mind soon boggles at the variety and intricacies of the rounding schemes that may be used for different applications. In addition to introducing different techniques, this article provides real-world examples of the types of errors associated with the different rounding schemes applied at various stages throughout a digital filter.


Here is the link to the article: