12-05-07

How to choose the right RTOS

Since today we all want to install an OS on an FPGA let's have a look at a nice article on Programmable Logic Deisgnline:

 

link: http://www.pldesignline.com/howto/showArticle.jhtml?artic...

 

This article helps you with making a choose for a RTOS for your FPGA/ASIC platform.

11:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: asic, platform, rtos, fpga |  Facebook |

12-03-07

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

Link: http://www.fpgajournal.com/news_2007/03/20070312_03.htm

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of CoVer™, a Windows®-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7™ core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance

Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop

The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

Components

The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

* Aldec Active-HDL (Designer Edition) mixed-language simulator
* Actel’s CoreConsole IP Deployment Platform
* Actel Libero® Integrated Design Environment (IDE) – Gold edition
* Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
* Software development system, including Actel’s SoftConsole program development environment

Availability

CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com.

About Aldec

Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com.

CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

22:09 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, actl, co-verification, actel, fpga, hw sw, asic, vhdl |  Facebook |

07-01-07

The Top-10 Programmable Logic "How To" articles of 2006

As most of the visitors of this blog are interested in FPGA and their technology I hereby put some of the most interesting articles about technology about FPGA's and everything around (or inside ) them. Enjoy this links 

 

#10 Alternative computing solutions, from single cores to arrays of 'things'
There are many ways of performing computations, including single CPU or DSP processors (chips or cores), multiple processors, arrays of "things", and "great big piles of gates."

#9 The state-of-play in multi-processor and reconfigurable computing
When a conventional processor (core) cannot meet the needs of a target application, it becomes necessary to evaluate alternative solutions such as multiple cores and/or configurable cores.

#8: How to take advantage of partial reconfiguration in FPGA designs.
The capability of designs to leverage partial reconfiguration opens doors to a whole host of applications.

#7: How to invert three signals with only two NOT gates (and *no* XOR gates): Part 2.
In part two of this article, we consider a dynamic solution to our original problem (using a ring oscillator and other "stuff"); also, we learn how to implement a NOT gate using four AND gates!

#6: FPGA Architectures from 'A' to 'Z' – Part 2.
If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.

#5: All About FPGAs.
An industry expert examines field-programmable gate arrays (FPGAs), including current and forthcoming architectures, technologies, and software tools.

#4: How to implement a digital oscilloscope in Structured ASIC fabric.
Structured ASICs provide quicker time-to-market and lower development costs than standard ASICs, while also providing higher performance and lower unit costs than FPGAs.

#3: How to invert three signals with only two NOT gates (and *no* XOR gates): Part 1
Even for hardened logic designers, these solutions will delight and entertain; also, there's a new "Brain Boggler" to be pondered.

#2: FPGA architectures from 'A' to 'Z' – Part 1
If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this two-part tutorial explains all.

#1: An introduction to different rounding algorithms
The mind soon boggles at the variety and intricacies of the rounding schemes that may be used for different applications. In addition to introducing different techniques, this article provides real-world examples of the types of errors associated with the different rounding schemes applied at various stages throughout a digital filter.

 

Here is the link to the article:

http://www.pldesignline.com/196801547?cid=RSSfeed_program...

20-12-06

I just came across a list of European Fabless Semiconductor companies

ACCO

Acuid Corporation

Alpha Microelectronics

Alphamosaic (Now purchased by Broadcom)

Anadigm

Ansem

ART VPS

ASICOM Technologies

Aspex Technology

AudioCodec

AXEON Limited

Bluechip Communications

BroadLight

Cambridge Semiconductor

Chipcon

ClearSpeed

Cologne Chip

Communication and Control Electronics Ltd (C&CE)

CopperGate Communication

CSR Ltd (Cambridge Silicon Radio)

Cyan Technology

Dialog Semiconductor

DiBcom (Digital Broadband Communications)

Digital Communication Technologies (DCT)

Elixant

EZchip Technologies

Frontier Silicon

HELIC

Helix

HyWire

IC4IC (Intellectual Capital for Integrated Circuits)

Icera Semiconductor

Imagination Technologies

Imsys

INCIDE

Inova Semiconductors

Inside Contactless

ITRAN Communications

Kailight Photonics

Lycium Networks

Melexis

Metalink

MicroEmissive Displays (MED)

Modem Art

M-Systems

MystiCom

Nanolayers

NemeriX

NeuriCam

NewLogic Technologies

Nordic VLSI

NoyoTec

Oasis Silicon Systems

Oplus Technologies

Oxford Semiconductor

PACT XPP Technologies

Passive Technologies

Phyworks

picoChip Designs

RFWaves

Runcom Technologies

Saifun Semiconductors

SIDSA

Silicon Construction Sweden

SOISIC

Spirea

Swindon Silicon Systems

SwitchCore

Tak'Asic

TeraChip

Tpack

TransChip

TRINAMIC Microchips

TTP Com

Wireless Experience Wep

Wisair

Wolfson Microelectronics

Xemics

Xignal Technologies

ZMM Technologies

 

I copy/pasted in out of a document from PWC (PriceWaterHouseCoopers).

 

here is the link to the document titled:

European Semiconductors Fabless Review:

Blurring Business Models (http://www.pwc.com/images/tech/Fabless.pdf)

11:43 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fabless, asic, melexis |  Facebook |