VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )


-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;


Here is the code for a simple testbench:


-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.


    variable good : boolean;
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
  end process;

  -- Parm Assignment Block
  AssignParms : process
    tb_ParameterInitFlag <= true;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
  end process;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance


  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;


I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.


I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:



13:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: synplify, fpga, libero ide, example, modelsim, vhdl, hardware, programming, actel, actl |  Facebook |


Actel Announces First Quarter 2007 Revenues Options

Mountain View, Calif. -- Apr 24, 2007 --  Actel Corporation (NASDAQ:
ACTL) today announced net revenues for the first quarter of 2007,
which ended April 1, 2007. No additional financial results for the
first quarter will be available until after completion of the ongoing
review of the Company's historical stock option practices and related

Net revenues for the first quarter of 2007 were $48.6 million, up 5
percent from the first quarter of 2006 and up one percent from the
fourth quarter of 2006.

Revenue Outlook - Second Quarter 2007

The Company believes that second quarter revenues will be flat
sequentially, plus or minus two percent. This is a "forward-looking
statement" within the meaning of the Private Securities Litigation
Reform Act of 1995 and should be read with the "Risk Factors" in the
Company's most recent Form 10-Q, which can be found on Actel's web
site, www.actel.com. The Company's quarterly revenues are subject to a
multitude of risks, including general economic conditions and a
variety of risks specific to Actel or characteristic of the
semiconductor industry, such as fluctuating demand, intense
competition, rapid technological change and related intellectual
property and international trade issues, wafer and other supply
shortages, and booking and shipment uncertainties. These and the other
Risk Factors make it difficult for the Company to accurately project
quarterly revenues, and could cause actual results to differ
materially from those projected in the forward-looking statement.
Actel does not assume, and expressly disclaims, any duty to update the
forward-looking statement and Risk Factors.

Stock Option Review

As previously announced:

On September 22, 2006, a Special Committee of the Board of Directors
of Actel, composed of independent directors and assisted by
independent counsel, was appointed to review the Company's historical
stock option grant practices and related accounting.
Actel voluntarily informed the staff of the Securities and Exchange
Commission ("SEC") about the internal review and is cooperating with
the SEC in its informal inquiry.
On January 18, 2007, Actel's management concluded that shareholders
and other investors should no longer rely on the Company's financial
statements and the related reports or interim reviews of Actel's
independent registered public accounting firm and all earnings press
releases and similar communications issued by the Company for fiscal
periods commencing on or after January 1, 1996.
On January 30, 2007, the Special Committee presented its preliminary
findings to the Board of Directors. The preliminary findings are
described in a Current Report on Form 8-K filed by Actel on February
1, 2007.
On March 9, 2007, the Special Committee delivered its final report to
the Board of Directors.
Working with its independent registered public accounting firm, the
Company is evaluating corrections to measurement dates and other
related accounting issues and is quantifying the financial and tax
impact of those corrections and related issues. In lieu of amending
its prior SEC filings to restate financial statements, Actel intends
to include in its Annual Report on Form 10-K for the fiscal year ended
December 31, 2006, the comprehensive disclosure outlined in guidance
posted by the SEC Chief Accountant's Office on January 16, 2007.
The Company has received notices from The Nasdaq Stock Market
("Nasdaq") of staff determinations that Actel is not in compliance
with the requirement for continued listing set forth in Nasdaq
Marketplace Rule 4310(c)(14), under which listed companies must file
all required SEC reports, and Rules 4350(e) and 4350(g), under which
companies must hold an annual meeting of shareholders, solicit
proxies, and provide proxy statements to Nasdaq. On February 16, 2007,
a Nasdaq Listing Qualifications Panel ("Panel") granted the Company's
request for continued listing, subject to certain conditions.
On April 2, 2007, the Nasdaq Listing and Hearing Review Council
("Listing Council") stayed the February 16, 2007, decision of the
Panel pending a review by the Listing Council of the merits of the
Panel's decision. By June 20, 2007, the Nasdaq Listing Qualifications
Department will provide the Listing Council with an updated
qualifications summary sheet and any additional information that staff
believes would assist the Listing Council in its review of this
matter. The Company may submit any additional information that it
wishes the Listing Council to consider by June 29, 2007.

The Company will not announce full financial results for the first
quarter of 2007 until it files its Quarterly Report on Form 10-Q for
the fiscal quarter ended April 1, 2007. The Company intends to file
its delinquent SEC periodic reports, including any required
restatements, and solicit proxies and hold an annual shareholders'
meeting as soon as practicable.

21:14 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: 2007, actl, california, actel, revenues, mountain view, fpga |  Facebook |


Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

Link: http://www.fpgajournal.com/news_2007/03/20070312_03.htm

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of CoVer™, a Windows®-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7™ core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance

Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop

The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.


The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

* Aldec Active-HDL (Designer Edition) mixed-language simulator
* Actel’s CoreConsole IP Deployment Platform
* Actel Libero® Integrated Design Environment (IDE) – Gold edition
* Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
* Software development system, including Actel’s SoftConsole program development environment


CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com.

About Aldec

Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com.

CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

22:09 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, actl, co-verification, actel, fpga, hw sw, asic, vhdl |  Facebook |