18-09-07

Opendirectory of ACTEL animated presentations

The title says it all; check the following link:

http://www.icvclients.com/actel/

 

Contents:

 ARMChina/               19-Dec-2006 09:09      - 
ARMIntro/               30-Nov-2006 16:52      - 
ARMinFusion/            15-Dec-2006 11:11      - 
Coremp7/ 22-May-2007 11:36 - CortexWebcast/          22-May-2007 09:18      - 
FER_training/           30-Jul-2007 07:40      - 
FiveMinProc/            30-Mar-2007 11:17      - 
FusionChina/            19-Dec-2006 09:44      - 
FusionIntro/            20-Nov-2006 12:40      - 
IglooChina/             22-May-2007 10:05      - 
ProcessorFlow/          30-Mar-2007 11:23      - 
RAD_update/             31-Jul-2007 08:11      - 
SmartDesign/            20-Jun-2007 14:28      - 
TrueFlash/              22-May-2007 09:18      - 
actel_power/            27-Aug-2007 15:26      - 
automotive/             27-Aug-2007 15:35      - 
coreABC/                22-May-2007 09:23      - 
email_images/           30-Jul-2007 12:16      - 
fusion_architecture/    31-Jul-2007 08:15      - 
igloo_2006/             22-May-2007 11:34      - 
low_cost_system_mana..> 27-Aug-2007 15:24      - 
microtca_2006/          22-May-2007 11:33      - 
proasic_3/              31-Jul-2007 07:23      - 
q1_2007/                26-Apr-2007 18:32      - 
q2_2006/                28-Jul-2006 17:33      - 
q2_2007/                31-Jul-2007 05:42      - 
q3_2006/                30-Oct-2006 09:56      - 
q4_2006/                06-Feb-2007 11:10      - 
security-old/           26-Jan-2007 17:22      - 
security/               23-Feb-2007 10:56      - 
smartdesign_pt2/        27-Jul-2007 04:57      - 
space/                  30-Jul-2007 04:57      - 
sxa_customer/           31-Jul-2007 07:37      - 
technical_support/      31-Jul-2007 08:03      - 

16:58 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, coreabc, animated, tutorial, igloo, arm, fusion |  Facebook |

29-08-07

Soon Actel FPGA's for the mass!!!

Today I have read the following article: http://www.pldesignline.com/201802670?cid=RSSfeed_program...

This looks like a nice module; especially for solution providers that don't make their own boards. This board is also a nice tool to use in the education sector like in the Universities. 

 

I am convinced that for learning purposes of FPGA programming it is better to start with the design flow for ACTEL fpga's. Every step you make is clear in their Libero IDE toolchain.

 

I hope that the price will soon fall down of that module so that their is an change to create a more community of ACTEL FPGA Developers.

 

09:47 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: fpga, actel, module, proasic3, community |  Facebook |

20-08-07

Install Linux on H3650 IPAQ

Today I am trying to install familiar linux on my IPAQ H3850 to have a handheld computer to write some regular software on to communicate with some of my ACTEL FPGA boards. More information will follow.

 

More information on: http://www.handhelds.org

 

 

 

 

17:04 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, linux |  Facebook |

16-08-07

CoreABC - Binary Counter

Another example of the binary counter implemented as a SoC on an ACTEL ProASIC3 FPGA by use of the CoreABC and CoreGPIO softcore microprocessor.

 Enjoy this educational example.

// http://mobile.skynetblogs.be

// Vincent Claes 

LOAD 1
$Main
APBWRT ACC 0 0
CALL $Wait500ms
ADD 1
APBWRT ACC 0 0
CALL $Wait500ms
JUMP $Main

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

 

12:14 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, coregpio, soc |  Facebook |

15-08-07

Another Example for CoreABC Programming on the ACTEL FPGA

Here is the code; I don't have many time at this moment so there is no information included :-) If you need some just reply to this post and I will explain the code.

 This program shows you a running led (only one time) everytime you enable the processor


$LedOff    IOWRT ACC
    CALL $Wait500ms
$LedOn    SHL0
    CALL $Wait500ms
    JUMP $LedOff

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

10:24 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: coreabc, fpga, actel |  Facebook |

19-06-07

Libero v8.0

I have just downloaded my copy of Libero Version 8.0. I have just started it for seeing the UI. The SmartDesign tool in the Libero IDE will be easy to use I think. Soon I will post here a small example on how to use it... I have other work to do at this time sorry guys ;-)

 

For the release notes see the following link: http://www.actel.com/download/software/libero/libero80rl....

 

 

A Project manager in Libero IDE whoohw!!!

 

SmartDesign will be amazing!

11:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: smartdesign, libero, actel, fpga, esl |  Facebook |

14-06-07

VHDL code for an 74-series ALU (the 74LS381 chip)

Hereby I give you my code of the 74LS381 IC, which is an ALU with 4-bits width.

 

The VHDL Code:

-- IC74381.vhd
-- Developed by Vincent Claes
-- claesvincent (at) gmail.com

-- http://mobile.skynetblogs.be
-- 2007 (c)
--
-- This version is a simlified version of the 74LS381 IC. It shows the main functionality in VHDL
-- It is developed for educational purposes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  s2  s1  s0  operation
--------------------------
--  L   L   L   clear
--  L   L   H   B minus A
--  L   H   L   A minus B
--  L   H   H   A plus B
--  H   L   L   A xor B
--  H   L   H   A + B
--  H   H   L   AB
--  H   H   H   PRESET  

entity IC74381 is
port(   a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        s: in std_logic_vector (2 downto 0);
        f: out std_logic_vector (3 downto 0)
);
end IC74381;

architecture arch of IC74381 is
signal BminusA,AminusB,AplusB,AxorB,AandB,AB: std_logic_vector(3 downto 0);
signal au,bv0,bv1,bv2,bv3: unsigned(3 downto 0);
signal p0,p1,p2,p3,prod: unsigned(7 downto 0);

begin

BminusA <=  std_logic_vector(signed(b)-signed(a));
AminusB <=  std_logic_vector(signed(a)-signed(b));
AplusB  <=  std_logic_vector(signed(a)+signed(b));
AxorB   <= a xor b;
AandB   <= a and b;

au  <=unsigned(a);
bv0 <=(others=>b(0));
bv1 <=(others=>b(1));
bv2 <=(others=>b(2));
bv3 <=(others=>b(3));
p0  <="0000" & (bv0 and au);
p1  <="000"&(bv1 and au) & "0";
p2  <="00" & (bv2 and au) & "00";
p3  <="0" & (bv3 and au) & "000";
prod<=((p0+p1)+(p2+p3));
AB<=std_logic_vector(prod(3 downto 0));

f   <=  "0000"      when s="000" else
        BminusA     when s="001" else
        AminusB     when s="010" else
        AplusB      when s="011" else
        AxorB       when s="100" else
        AandB       when s="101" else
        AB          when s="110" else
        "1111"; 
end arch;

 

 

The testbench code:

 

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    a : inout std_logic_vector(3 downto 0) := x"7";
    b : inout std_logic_vector(3 downto 0) := x"3";
    s : inout std_logic_vector(2 downto 0));

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 10 ns;
    s <= "101";
    wait for 10 ns;
    s <= "110";
    wait for 10 ns;
    s <= "111";
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 20 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal a : std_logic_vector(3 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal s : std_logic_vector(2 downto 0);
  signal f : STD_LOGIC_VECTOR(3 downto 0);

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (a => a,
              b => b,
              s => s);

  -- Instantiation of Model Under Test.
  IC74381_0 : entity work.IC74381
    port map (a => a,
              b => b,
              s => s,
              f => f);
end tbGeneratedCode;

 

Screenshot of the Simulation in ModelSim:

 

wave_IC74381

 

Please remember this code is written in 4bits width. And I show the results in HEX!!!

 

For educational purposes I also include the netlist view of my program:

 

netlistview_IC74381

 

13-06-07

VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )

 

-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
 port(
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
  );
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

begin
output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;

 

Here is the code for a simple testbench:

 

-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;

 

I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.

 

I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:

 

even_detector

13:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: synplify, fpga, libero ide, example, modelsim, vhdl, hardware, programming, actel, actl |  Facebook |

25-04-07

Actel Announces First Quarter 2007 Revenues Options

Mountain View, Calif. -- Apr 24, 2007 --  Actel Corporation (NASDAQ:
ACTL) today announced net revenues for the first quarter of 2007,
which ended April 1, 2007. No additional financial results for the
first quarter will be available until after completion of the ongoing
review of the Company's historical stock option practices and related
accounting.

Net revenues for the first quarter of 2007 were $48.6 million, up 5
percent from the first quarter of 2006 and up one percent from the
fourth quarter of 2006.

Revenue Outlook - Second Quarter 2007

The Company believes that second quarter revenues will be flat
sequentially, plus or minus two percent. This is a "forward-looking
statement" within the meaning of the Private Securities Litigation
Reform Act of 1995 and should be read with the "Risk Factors" in the
Company's most recent Form 10-Q, which can be found on Actel's web
site, www.actel.com. The Company's quarterly revenues are subject to a
multitude of risks, including general economic conditions and a
variety of risks specific to Actel or characteristic of the
semiconductor industry, such as fluctuating demand, intense
competition, rapid technological change and related intellectual
property and international trade issues, wafer and other supply
shortages, and booking and shipment uncertainties. These and the other
Risk Factors make it difficult for the Company to accurately project
quarterly revenues, and could cause actual results to differ
materially from those projected in the forward-looking statement.
Actel does not assume, and expressly disclaims, any duty to update the
forward-looking statement and Risk Factors.

Stock Option Review

As previously announced:

On September 22, 2006, a Special Committee of the Board of Directors
of Actel, composed of independent directors and assisted by
independent counsel, was appointed to review the Company's historical
stock option grant practices and related accounting.
Actel voluntarily informed the staff of the Securities and Exchange
Commission ("SEC") about the internal review and is cooperating with
the SEC in its informal inquiry.
On January 18, 2007, Actel's management concluded that shareholders
and other investors should no longer rely on the Company's financial
statements and the related reports or interim reviews of Actel's
independent registered public accounting firm and all earnings press
releases and similar communications issued by the Company for fiscal
periods commencing on or after January 1, 1996.
On January 30, 2007, the Special Committee presented its preliminary
findings to the Board of Directors. The preliminary findings are
described in a Current Report on Form 8-K filed by Actel on February
1, 2007.
On March 9, 2007, the Special Committee delivered its final report to
the Board of Directors.
Working with its independent registered public accounting firm, the
Company is evaluating corrections to measurement dates and other
related accounting issues and is quantifying the financial and tax
impact of those corrections and related issues. In lieu of amending
its prior SEC filings to restate financial statements, Actel intends
to include in its Annual Report on Form 10-K for the fiscal year ended
December 31, 2006, the comprehensive disclosure outlined in guidance
posted by the SEC Chief Accountant's Office on January 16, 2007.
The Company has received notices from The Nasdaq Stock Market
("Nasdaq") of staff determinations that Actel is not in compliance
with the requirement for continued listing set forth in Nasdaq
Marketplace Rule 4310(c)(14), under which listed companies must file
all required SEC reports, and Rules 4350(e) and 4350(g), under which
companies must hold an annual meeting of shareholders, solicit
proxies, and provide proxy statements to Nasdaq. On February 16, 2007,
a Nasdaq Listing Qualifications Panel ("Panel") granted the Company's
request for continued listing, subject to certain conditions.
On April 2, 2007, the Nasdaq Listing and Hearing Review Council
("Listing Council") stayed the February 16, 2007, decision of the
Panel pending a review by the Listing Council of the merits of the
Panel's decision. By June 20, 2007, the Nasdaq Listing Qualifications
Department will provide the Listing Council with an updated
qualifications summary sheet and any additional information that staff
believes would assist the Listing Council in its review of this
matter. The Company may submit any additional information that it
wishes the Listing Council to consider by June 29, 2007.

The Company will not announce full financial results for the first
quarter of 2007 until it files its Quarterly Report on Form 10-Q for
the fiscal quarter ended April 1, 2007. The Company intends to file
its delinquent SEC periodic reports, including any required
restatements, and solicit proxies and hold an annual shareholders'
meeting as soon as practicable.

21:14 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: 2007, actl, california, actel, revenues, mountain view, fpga |  Facebook |

09-04-07

Design example for ACTEL fpga's with ARM Cortex-M1

Link: http://www.electronicstalk.com/news/ank/ank280.html

 

Synplicity and ARM have signed a joint marketing and collaboration agreement that includes a reference methodology for the recently launched ARM Cortex-M1 processor - the first ARM processor specifically designed for implementation on FPGAs.

09:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, arm, fpga, reference design, cortex-m1, softcore, processor, synplicity |  Facebook |

19-03-07

Thursday 22/03/2007: "Analog meets Digital on snow" seminar

Thursday there is a ACAL (ACTEL representative for Belgium) seminar planned. Here are the topics that will be handled:

 

Agenda :
        08:30 - 09:00 : Registration + Breakfast
        09:00 - 09:05 : Welcome (Guy Maertens MD Acal Belgium)
        09:05 - 11:00 : Power (Jens Hedrich FAE Linear Technology)
        11:00 - 11:15 : Coffee Break
        11:15 - 12:00 : Data Conversion (Jens Hedrich FAE Linear Technology)
        12:00 - 13:00 : Bruegelian Buffet
        13:00 - 13:15 : Igloo Launch (Vaughan Price Managing Director Actel Europe)
        13:15 - 13:45 : New Technology Solutions (Patrizio Piasentin Regional Sales Manager Actel)
        13:45 - 14:30 : System Management, µTCA, MotorControl (Luca Cattaneo ETM Actel)
        14:30 - 14:45 : Coffee Break
        14:45 - 15:30 : Low Power Design Tricks (Luca Cattaneo ETM Actel)
        16:00 - 18:00 : Ski & Snowboard Session + Snacks
        18:15 - 19:00 : Appetizers and Prize Giving

 

More information can be found here:

http://www.acal.be/index.php?module=calendar&calendar...

22:01 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: acal, actel, snow, fpga, actel europe |  Facebook |

 

Actel and ARM Develop High-Performance 32-Bit Processor Optimized for FPGAs

Actel Offers New Cortex-M1 for Use in Flash-based M1 ProASIC3 and M1 Fusion Devices

MOUNTAIN VIEW, Calif., March 19, 2007 — Disclosing further details of its industry-standard processor portfolio, Actel Corporation (NASDAQ: ACTL) today announced the availability of its implementation of the ARM® Cortex™-M1 processor, a small, high-performance, 32-bit soft core co-developed by the companies for optimal use in field-programmable gate arrays (FPGAs). Removing the license and royalty fees typically associated with licensing models for industry-leading processor cores, Actel offers free access to advanced ARM processor technology to the broad marketplace. The free delivery of the Cortex-M1 processor for use in Actel's flash-based, M1-enabled Actel Fusion and ProASIC3 FPGAs provides system designers programmable flexibility and system-level integration, enabling the development of low-cost, high-performance systems.

"With the significant increase in the use of FPGAs as flexible, cost-effective platforms for the rapid design of high-quality embedded systems, the introduction of an FPGA-optimized ARM processor enables us to serve the growing needs of companies who require highly programmable solutions," said John Cornish, vice president, marketing, Processors Division, ARM. "The unprecedented security benefits and advanced features offered by Actel's flash-based FPGAs make these devices an ideal vehicle for our high-performance processor technology."

Rich Brossart, vice president, product marketing at Actel, added, "Evidenced by the success of our soft ARM7™ family processor core, designers continue to show great interest in implementing industry-standard 32-bit processor technologies in FPGAs. With the addition of the FPGA-optimized ARM Cortex-M1 processor, free of license and royalty fees, to our broad processor portfolio, system designers can select the solution that best meets their design requirements regardless of application or volume."

Cortex-M1 Processor and Actel's M1-Enabled FPGAs

Derived from ARM's three-stage Cortex-M3 processor pipeline, the highly configurable Cortex-M1 processor operates at up to 72 MHz in Actel's M1-enabled Fusion Programmable System Chip (PSC) or ProASIC3 FPGAs. Providing a good balance between size and speed for embedded applications, the core is able to be implemented in as few as 4300 tiles, roughly 20 percent of an M1A3P1000 ProASIC3 device or 30 percent of a mixed-signal M1AFS600 Actel Fusion PSC. The Cortex-M1 processor solution also connects to the industry-standard AHB bus, allowing designers to build a subsystem and easily add peripheral functionality to the processor.

With the increasing costs of application-specific integrated circuit (ASIC) design, designers can benefit from a Cortex-M1 processor-based implementation in an FPGA due to reduced design time and a lower cost of entry into system-on-chip design, particularly for lower volume applications. However, for designs that scale to ultra-high volumes, the 32-bit Cortex-M1 processor runs the industry-standard Thumb® instruction set and is upward compatible with the Cortex-M3 processor, providing an easy migration path to ASIC implementation.

Actel's flash-based FPGAs, the mixed-signal M1 Actel Fusion PSCs and low-cost M1 ProASIC3 devices, are virtually immune to tampering, assuring users that valuable IP will not be compromised or copied. The single-chip devices also provide the low power, firm-error immunity and live at power-up capabilities that are inherent to all Actel FPGAs.

Comprehensive Tool Support

The Cortex-M1 processor is supported by the comprehensive tools and knowledge that currently exists for the ARM architecture, far surpassing the level of support offered for proprietary processors. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment, and Actel Libero Integrated Design Environment—all available for free download from Actel's Web site. Actel's implementation of the Cortex-M1 processor is fully supported by the ARM RealView® Development Suite and RealView Microcontroller Development Kit. Third-party vendors, such as Aldec, CriticalBlue, CodeSourcery, IAR, ImpulseC and Keil™, an ARM Company, will also support the new processor with a host of tools—from compilers and debuggers to RTOS support.

Pricing and Availability

Actel's implementation of the Cortex-M1 processor will be available for early access in April. The M1A3P1000 ProASIC3 device and M1AFS600 Fusion PSC device will sample in Q3 2007 with production quantities in Q4 2007. Pricing for the M1 devices starts at $3.95. For further information about pricing and availability, please contact Actel or visit the company's Web site at www.actel.com .

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).

21:50 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, arm, 32-bit, softcore, core, ip, processor, actel, cortex-m1 |  Facebook |

ARM Extends Cortex Family With First Processor Optimized for FPGA

ARM Extends Cortex Family With First Processor Optimized for FPGA

The ARM Cortex-M1 processor enables OEMs to reduce development costs throughstandardization on a single architecture across FPGA, ASIC and ASSP

CAMBRIDGE, UK, March 19, 2007 — ARM [(LSE:ARM); (Nasdaq: ARMHY)] today announced the availability of the ARM® Cortex™-M1 processor – the first ARM processor designed specifically for implementation on FPGAs. The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers.

ARM and Actel will both be demonstrating the Cortex-M1 processor at the Embedded Systems Conference in San Jose, Calif., April 2-5.

The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor. The Cortex-M1 processor is supported by leading FPGA synthesis vendors, software development tools, and real-time operating systems, giving FPGA designers unprecedented choice and flexibility.

"Gartner Dataquest maintains that FPGAs/PLDs have a very bright future," said Bryan Lewis, research vice president, Gartner Dataquest. "We expect solid growth (15.7 percent) to resume in 2008 and forecast the FPGA/PLD market to outperform semiconductors from 2008 onward."1
"The Cortex-M1 processor extends the reach of the ARM architecture in the FPGA domain, and advances our goal of providing processor solutions for the entire digital world," said Graham Budd, EVP and general manager, Processor Division, ARM. "By leveraging ARM's vast installed user base in the ASIC/ASSP and microcontroller markets, along with support from our own RealView® family of tools as well as product support from the ARM Connected Community, the Cortex-M1 processor will deliver significant savings to OEMs in terms of software development resources, tools, and training."

Actel has licensed the Cortex-M1 processor and will make it available at no additional cost to their customers. The FPGA-optimized Cortex-M1 processor offers users of Actel's flash-based M1-enabled Actel Fusion Programmable System Chips and ProASIC3 FPGAs a compact and efficient processor satisfying the requirements of a wide range of end applications. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment and Actel Libero Integrated Design Environment – all available for free download from Actel's website.

"Following the success of our ARM7™ family-based solutions, Actel worked closely with ARM to optimize its Cortex-M1 processor for FPGA implementation from the ground up, making it an extremely valuable addition to our growing processor library," said Rich Brossart, vice president, product marketing, Actel. "Free of the contract negotiations and fees typically associated with industry-standard processor cores, Actel will make the Cortex-M1 processor available to those companies who desire highly programmable solutions regardless of application or volume."

Tools and Peripherals Support

The Cortex-M1 processor will be fully supported by forthcoming releases of the ARM RealView® Development Suite and RealView Microcontroller Development Kit. The RealView Development Suite will include a complete instruction set system model (ISSM) allowing developers to create and test applications for the Cortex-M1 processor out of the box. Developers can easily customize the RealView Development Suite's debugger to visualize and interact withperipherals added around a Cortex-M1 processor, and will also be able to connect and debug applications running on Cortex-M1 silicon using ARM's high-performance RealView ICE and ULINK®2 run control units.

System performance and design turn around time are boosted further with ARM AMBA® compliant PrimeCell® peripheral IP, including ARM's latest ultra-efficient microDMA (PL230).
ARM Connected Community Partners, including CodeSourcery, Express Logic, IAR Systems, Mentor Graphics Inc., Micrium and Synplicity will all support the Cortex-M1 processor. For improved flow integration, the Cortex-M1 processor deliverables will include an IP description conforming to the IP-XACT standard from The SPIRIT Consortium.

Low area, high frequency and ease of use

The ARM Cortex-M1 processor is a streamlined three-stage 32-bit RISC processor that implements a subset of the popular, high density Thumb®-2 instruction set. This enables both the processor and software footprint to meet the area budget of the smallest FPGA devices, while retaining compatibility with Thumb code for any ARM processor from the ARM7TDMI® processor upwards.The Cortex-M1 processor is capable of more than 170 MHz, whilst occupying less than 15 percent area of popular low-cost FPGA devices. Despite being the smallest processor in the Cortex family, the Cortex-M1 processor can deliver 0.8 DMIPS/MHz. Typical applications for the Cortex-M1 processor on FPGAs include embedded control, communications, networking and aerospace.

More information on ARM solutions in FPGA is available from www.arm.com/fpga.

Availability

Free of license and royalty fees, Actel's implementation of the Cortex-M1 processor will be available for early access in April via the Actel website www.actel.com. The M1-enabled ProASIC3 and Actel Fusion PSC devices will sample in Q3 2007.

The ARM Cortex-M1 processor RTL and associated EDA views optimized for a range of FPGA vendor devices including Actel, Altera, Lattice and Xilinx will be available for license by OEMs in 2Q'07.

About the ARM Cortex Family of Processors

The three series in the ARM Cortex family enable chip manufacturers and OEMs to standardize around a single architecture from low-end microcontrollers to high-performance applications processors. Featuring Thumb-2 technology, the ARM Cortexfamily significantly reduces development costs and increases enterprise efficiency.

  • ARM Cortex-A Series: Applications processors for complex OS and user applications
  • ARM Cortex-R Series: Embedded processors for real-time systems
  • ARM Cortex-M Series: Deeply embedded processors optimized for microcontroller and low-cost applications

About ARM
ARM designs the technology that lies at the heart of advanced digital products, frommobile, home and enterprise solutions toembedded and emerging applications. ARM's comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphics processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.

About the ARM Connected Community
The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions. For more information, please visit http://www.arm.com/community.

ENDS

1. Gartner, Inc., "Forecast: ASIC/ASSP, FPGA/PLD and SLI/SOC Applications, Worldwide, 2002-2010 (4Q06 Update)", by John Barber and Bryan Lewis, December 4, 2006.

ARM, Thumb, RealView, PrimeCell and ARM7TDMI are registered trademarks of ARM Limited. Cortex and ARM7 are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; and ARM Physical IP, Inc.; and ARM Norway AS.

Contact: Stephanie Mrus, Actel Corporation, 650.318.4614

21:49 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, fpga, actel, cortex-m1, oem |  Facebook |

17-03-07

ACTEL FPGA developers community

I just opened the ACTEL FPGA developers community which is a mailinglist of all Actel FPGA developers. It will be a meeting place from ACTEL FPGA developers all over the world. If you would like to know where people are working on with ACTEL fpga's just join the mailinglist.

 

 

 

Bètaversie van Google Discussiegroepen
ACTEL FPGA developers
Naar deze groep gaan

 

 

 

Bètaversie van Google Discussiegroepen
Aanmelden bij ACTEL FPGA developers
E-mailadres:
Naar deze groep gaan

14:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, developers, community, fpga |  Facebook |

16-03-07

VHDL code for 7segment display

For some of your FPGA projects it can be usefull to get an 7-segment display driver circuit. There is no 7-segment LCD on my ACTEL fpga boards but I am sure you guys know how to work around this topic with your hands ;-)

 

 

VHDL code listing:

 

LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY seg7 ISPORT (
D       : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);  -- BCD input      
S       : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- 7 segment outputsEND seg7;
ARCHITECTURE display OF SEG7 ISBEGINs <=  	"1000000" WHEN d = "0000" ELSE       
      	"1111001" WHEN d = "0001" ELSE       
	"0100100" WHEN d = "0010" ELSE       
	"0110000" WHEN d = "0011" ELSE       
	"0011001" WHEN d = "0100" ELSE       
	"0010010" WHEN d = "0101" ELSE       
	"0000010" WHEN d = "0110" ELSE       
	"1111000" WHEN d = "0111" ELSE       
	"0000000" WHEN d = "1000" ELSE       
	"0010000" WHEN d = "1001" ELSE       
	"0001000" WHEN d = "1010" ELSE       
	"0000011" WHEN d = "1011" ELSE       
	"1000110" WHEN d = "1100" ELSE       
	"0100001" WHEN d = "1101" ELSE       	
	"0000110" WHEN d = "1110" ELSE       
	"0001110";                     
END display;

13:05 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: fpga, vhdl, actel, 7-segment |  Facebook |

12-03-07

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

Link: http://www.fpgajournal.com/news_2007/03/20070312_03.htm

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of CoVer™, a Windows®-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7™ core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance

Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop

The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

Components

The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

* Aldec Active-HDL (Designer Edition) mixed-language simulator
* Actel’s CoreConsole IP Deployment Platform
* Actel Libero® Integrated Design Environment (IDE) – Gold edition
* Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
* Software development system, including Actel’s SoftConsole program development environment

Availability

CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com.

About Aldec

Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com.

CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

22:09 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, actl, co-verification, actel, fpga, hw sw, asic, vhdl |  Facebook |

Arasan Chip Systems Extends USB IP Offerings to Actel’s CompanionCore Program

Source: http://www.fpgajournal.com/news_2007/03/20070306_02.htm

 

SAN JOSE, Calif.--(BUSINESS WIRE)--Arasan Chip Systems, Inc. (“Arasan”), a leading supplier of reusable intellectual property (IP) cores, semiconductors and design services, today announced that it has joined Actel Corporation’s CompanionCore Alliance Program. Arasan has optimized its USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores for use with Actel’s flash-based, single-chip Actel Fusion, IGLOO, ProASIC3/E and ProASIC Plus field-programmable gate arrays (FPGAs). With these USB IP offerings, system designers have access to proven building blocks to streamline design and development, shorten time to market and reduce design costs and risks.

Actel CompanionCore products offer seamless implementation through Actel's suite of internal and third-party EDA development tools, documentation, and quality service and support, thereby streamlining the design process. Specific FPGA target data is available for each IP core on the CompanionCore Web site at http://www.actel.com/products/partners/companioncore/.

“We are excited about the opportunity to partner with Actel in its CompanionCore program,” said Kevin Walsh, vice president of marketing at Arasan Chip Systems. “Our customers can confidently use these USB cores, and others that we intend to put into the program, knowing we have done all the work to optimize them for use in Actel’s FPGAs.”

Rich Brossart, Actel vice president, product marketing said, "Arasan’s USB IP solutions complement Actel's flash-based devices, including the company’s innovative Actel Fusion, IGLOO, and ProASIC3/E FPGAs. For customers requiring USB connectivity, the addition of Arasan’s USB 2.0 Host, 2.0 Hub, 2.0 Device and OTG cores to the Actel CompanionCore program will enhance designer productivity and versatility while reducing time to market."

Total Technology Solution

Arasan provides a total technology solution to all its licensees, including IP source code, a test environment, sample device drivers, synthesis scripts, and complete technical documentation. The total technology solution also includes optional product design development tools like the hardware validation platform and software targeted for Linux. Custom bus integration services are offered to integrate the IP in a customer specific manner. Available for purchase, Arasan’s validation platform is a stand-alone board used to ease compliance testing of as well as prototyping, including driver development.

Pricing and Availability

Licenses for the USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores are available from Arasan in either synthesizable RTL or Actel-targeted netlist formats. The USB cores are available under special license terms. For more information on these IP cores, please visit Arasan at http://www.arasan.com or Actel at http://www.actel.com/products/ip/.

About Arasan

Arasan Chip Systems Inc. founded in 1995, is a leading supplier of Reusable Intellectual Property (IP’s) cores, semiconductors and electronic design services. Arasan’s product portfolio is focused on Bus Interfaces and includes IP’s for USB 1.1 & 2.0, PCI, SDIO and CE-ATA technologies. Arasan’s products and services enable businesses to develop and leverage product design and development. Arasan Chip Systems has been an executive member of SD Card Association since 2001, MMCA since 2003 and CE-ATA since 2004. Arasan is headquartered in San Jose, California, with design centers in India and support options available in Taiwan, China & Europe. Licensees of Arasan’s USB IP include companies like TI, Cisco, NEC, Staccato, Los Alamos National Laboratory, and General Atomics.

Visit: www.arasan.com for more product information.

02-03-07

Binary Counter on ACTEL ProASIC3 FPGA by use of CoreABC

I have just created a binary counter on the CoreABC softcore from ACTEL (see code below). Create the project from coreconsole (CoreABC, CoreGPIO and CoreAPB) in the latest post on this blog and put the next lines of code into the softcore. enjoy it!

 

 

// Created by Vincent Claes

// If you want to use please add a comment on my blog

// http://mobile.skynetblogs.be

   

    JUMP $Main

$Main
    WAIT WHILE INPUT0
$LedOff   
    LOAD 0
$LedOn
    APBWRT ACC 0 0
    INC
    CALL $Wait500ms
    JUMP $LedOn  
    CALL $Wait500ms
    JUMP $LedOff

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

22:37 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, coregpio, coreapb, binary counter, proasic3 |  Facebook |

Blinking leds by use of CoreABC, CoreGPIO and CoreAPB

According to the technical contacts I have within ACTEL it is not possible at this time to write the value you have in the accumulator to the parallel outputs on the softcore (CoreABC). In order to do something like this you have to experiment like me with the following cores in your coreconsole: CoreABC, CoreGPIO and CoreAPB.

 

Check out my set-up in coreconsole:

CoreABC_CoreGPIO_CoreAPB

The program I have placed into the hard-tiles of the CoreABC are the following lines:

 
    JUMP $Main

$Main
    WAIT WHILE INPUT0
$LedOff    APBWRT DAT 0 0 1
    CALL $Wait500ms
$LedOn    APBWRT DAT 0 0 3
    CALL $Wait500ms
    JUMP $LedOff
$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN
 
 
With thanks to ACTEL corporation for bringing us the CoreABC softcore processor and example 1 of this great softcore
 
Here we use the CoreABC processor as it is designed for... being a Master on the APB bus on our ACTEL fpga. the CoreGPIO is a slave core on this APB bus.
 
I implemented this program on my ProASIC3 A3P250 PQ208ES 0539 FPGA and the board I used for this is the A3PE-A3P-EVAL-BRD1 REV3.
 
Enjoy this sample.....
 

21:40 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: coreabc, actel, coregpio, coreapb, proasic3 |  Facebook |

27-02-07

Running Led Continious Mode

Hi all,

 

If you want to expand the latest project 'running led' to continious mode this is very easy to do:

 

just do the following things: in your 'root vhdl file' change the following lines of code:

 

entity ARM7BOARD_CoreABC_EXPERIMENT is
    -- Port list
    port(
        -- Inputs
        PCLK : in std_logic;
        -- Outputs
        IO_OUT : out std_logic_vector(7 downto 0)
    );
end ARM7BOARD_CoreABC_EXPERIMENT;

 

Where the inputs are listed remove the NSYSRESET input.

 

In the Code also change the Port Map of the RTL code (look at the line NSYSRESET; I force it to be 1 that's the trick ):

-- Port map
        port map(
            -- Inputs
            INITADDR => (others => '0'),
            INITDATA => (others => '0'),
            INITDATVAL => '0',
            INITDONE => '0',
            INTREQ => '0',
            IO_IN => (others => '0'),
            NSYSRESET => '1', -- I removed: NSYSRESET => NSYSRESET,
            PCLK => PCLK,
            PRDATA => (others => '0'),
            PREADY => '1',
            -- Outputs
            INTACT => open,
            IO_OUT => IO_OUT,
            PADDR => open,
            PENABLE => open,
            PRESETN => open,
            PSEL => open,
            PWDATA => open,
            PWRITE => open
        );

 

 

Connect the Clock to pin W17 and the IO to the 8 led's on the board.

 

Have fun with it

09:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, vhdl, example, program, sample |  Facebook |

Running Led Program for CoreABC

I did a new sample program for the CoreABC from Actel (I progammed this on my M7A3PE600 FPGA. This program is a running led be sure to press the NSYSRESET button to run the program.

 

In your CoreConsole Project You just have to put a CoreABC softcore CPU and bring out IO, PCLK and NSYSRESET to the Top Level.

 

On the ARM7 Board you can connect PCLK to Pin W17, IO to the Led's and for instance NSYSRESET to pin U3

 

$Main
    WAIT WHILE INPUT0

// Running LED
$LedOff    IOWRT 0
    CALL $Wait500ms
$LedOne    IOWRT 1
    CALL $Wait500ms
$LedTwo    IOWRT 2
    CALL $Wait500ms
$LedThree  IOWRT 4
    CALL $Wait500ms
$LedFour   IOWRT 8
    CALL $Wait500ms
$LedFive   IOWRT 16
    CALL $Wait500ms
$LedSix    IOWRT 32
    CALL $Wait500ms
$LedSeven  IOWRT 64
    CALL $Wait500ms
$LedEight  IOWRT 128
    CALL $Wait500ms
    JUMP $LedOff

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETUR

08:58 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: coreabc, actel, fpga, code, arm7 |  Facebook |

19-02-07

Blinking Led on ProASIC3 by use of CoreABC microcontroller

The next few lines are an introduction (if you like: a step-by-step guide, a tutorial) on how to use the CoreABC processor core on a ProASIC3 (A3PE-A3P-EVAL-BRD1) board. It shows you how to set up the core, how to copy/paste a working example program and how to use this program.

 

Enjoy it!

 

The first thing you have to do is start up the CoreConsole tool from ACTEL. You have to create a new project for this tutorial. In this project place 1 CoreABC block on the 'workspace'. After you have done this you have to make some settings: like there are: Connecting PCLK, NSYSRESET and IO to the Top level of your design. Another thing you have to do is configuring the softcore for using it with ProASIC3 FPGA's. (see also screenshots below).

 

 

 

 

On the second screenshot be sure you click the 'Program' Tab and put the following code in it:

 

JUMP $Main

 

 

$Main

    WAIT WHILE INPUT0

 

 

$LedOff    IOWRT 0

    CALL $Wait500ms

$LedOn    IOWRT 1

    CALL $Wait500ms

    JUMP $LedOff

 

$Wait500ms

    CALL $Wait100ms

$Wait400ms

    CALL $Wait100ms

$Wait300ms

    CALL $Wait100ms

$Wait200ms

    CALL $Wait100ms

$Wait100ms

    CALL $Wait20ms

$Wait80ms

    CALL $Wait40ms

$Wait40ms

    CALL $Wait20ms

$Wait20ms

    CALL $Wait10ms

$Wait10ms

    NOP

    LOADLOOP 34998

$Wait10msInner

    DECLOOP

    JUMP IFNOT LOOPZ $Wait10msInner

    RETURN

 

 

 

After this you just have to set up a new project in Libero IDE and import the core in this project (see screenshot).

 

Normally there are no green icons on your programming way yet (I took this screenshot after I had fully programmed my fpga).

 

Hit the Synthesis tool (Synplicity Actel Edition) and push the Run button in this program.

 

After this step you have to use the Place&Route tool. Be sure to make the following settings:

 

Remember that pin 26 is the clock on this Actel ProASIC3 board.

After you have created the stpl file from the Place&Route tool you can Program the FPGA by use of the FlashPro Tool

 

 

 

When you want to test the program you just have created just press the SW1 button on your board.

 

Enjoy this tutorial on implementing the CoreABC softcore on a ProASIC3 FPGA.

 

(The problem I had the first time I tried this was that I didn't connect the NSYSRESET pin to the top level).

 

I used an ProASIC3 A3P250 PQ208ES 0539 FPGA.

 

 

For Screenshots please see the following WORD document: Screenshots

 

22:08 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: softcore, fpga, coreabc, actel, tutorial, proasic3 |  Facebook |

30-01-07

Actel Champions Embedded Systems Designers with Broad Range of Industry-Standard Processor Solutions

I copy/paste this article to my blog because I like Actel FPGA and would like to promote this wonderfull things.
 
Actel Contact:
Stephanie Mrus
Actel Corporation
650-318-4614
stephanie.mrus@actel.com
www.actel.com
Actel Media Contact:
Shannon Jamison
Porter Novelli
408-369-4600 x630
shannon.jamison@porternovelli.com

Actel Champions Embedded Systems Designers with Broad Range of Industry-Standard Processor Solutions

Company Expands Highly Configurable Offering with Industry’s Smallest Soft Micro and New 8051 Controller Core

MOUNTAIN VIEW, Calif., January 29, 2007 — Delivering on its strategy to support embedded systems designers with a comprehensive portfolio of processor solutions, Actel Corporation (NASDAQ: ACTL) today introduced two free controller cores; the small, easy-to-use CoreABC and the configurable Core8051s. These cores complement the company’s existing library of industry-standard options, including a variety of ARM, 8051 and LEON processor solutions, optimized for Actel’s field-programmable gate arrays (FPGAs). In addition to third-party tools and capabilities, Actel also offers a comprehensive development environment, boards and reference designs to support its processor offerings. This ecosystem of tools and support enable Actel customers to get system-level products to market quickly and reduce cost and risk.

"The abundance of software and support available for industry-standard architectures eliminates the pain typically associated with adopting proprietary technologies," said Rich Brossart, vice president, product marketing at Actel. "Our growing processor portfolio enables embedded systems designers to select the best processor for their application and combine it with the core benefits offered by Actel’s flash-based FPGAs – ease of design, reprogrammability, and reduced development cost and risk."

Brossart continued, "Moving forward, we plan to continue the development of optimized processor solutions based on industry-standard architectures, enabling customers to further exploit the processors and tools they are familiar with when using Actel's innovative FPGAs."

Actel Expands Processor Library with Free, Easy-to-Use Cores

A powerful and easy-to-use solution for a broad range of embedded control applications, Actel's CoreABC is the industry's smallest and first RTL-programmable soft micro for FPGAs. The free controller features deterministic operation, very fast I/O response (less than 100 nanoseconds) and supports the advanced peripheral bus (APB) interface. Designers are able to use CoreABC in small Actel devices, such as the flash-based, low-cost A3P030 ProASIC3 device, because the free controller can be implemented in as few as 241 tiles and used without RAM or ROM resources. Implementation starts at less than 10 cents per instantiation.

Compatible with the industry-standard 8051 ASM51 instruction set, Core8051s allows designers to take advantage of the vast array of existing industry tools, knowledge and application software for the 8051 architecture. The controller, a higher performance version of the company's popular Core8051, features one clock per instruction throughput and supports a range of configurable peripheral functions. Core8051s connects to the APB bus for easy integration with other APB peripherals using Actel's CoreConsole tool.

Software, Support Critical to Design Success

To support its broad portfolio of processor solutions, Actel delivers a comprehensive development environment, including the Libero Integrated Design Environment (IDE), CoreConsole IP deployment platform, and SoftConsole software program development environment, as well as boards and reference designs. The processor cores are also supported by third-party tools and capabilities – from highly efficient C-compilers and co-verification solutions to advanced hardware acceleration. Key partners and third-party suppliers include Aldec, CriticalBlue, IAR, ImpulseC, and Keil.

Like all Actel processors, the two new free cores operate with the industry-standard AMBA bus interface enabling flexible, cost-effective system-on-chip (SoC) solutions across a broad range of markets and applications. Intellectual property (IP) vendors worldwide support the AMBA bus with a large number of peripheral IP cores, enabling designers to find and implement the specific functional elements needed for their embedded designs.

Pricing and Availability

Actel's DirectCore processors, including the new CoreABC and Core8051s, are available free of charge via Actel's CoreConsole software. The cores can be used in Actel single-chip FPGAs, including the Actel Fusion™, IGLOO™ and ProASIC3™ families. The fault-tolerant LEON3 processor core, optimized for Actel's military, aerospace and high-reliability customers, is available from Actel's CompanionCore partner Gaisler Research. For more information, please visit www.actel.com/products/ip.

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).

The Actel, Actel Libero, Actel IGLOO, Actel ProASIC3 and Actel Fusion names and logos are trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners.

 

Link: http://www.actel.com/company/press/2007/1/29

 

23:27 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, igloo, libero, proasic3, leon, arm, 8051, core8051s, coreabc |  Facebook |

23-01-07

At least: ACTEL FPGA's for non-big companies

Read this article: http://www.sys-con.com/read/326169.htm

 

I hope this will contribute to the rise of an 'ACTEL FPGA community' with more Application Notes, Open-source stuff, development boards, website and other 'non-ACTEL' Actel FPGA stuff'.

 

MANSFIELD, Texas and MOUNTAIN VIEW, Calif., Jan. 22 /PRNewswire-FirstCall/ -- Mouser Electronics, Inc., the fastest growing distributor in the electronics industry, and Actel Corporation , the leading supplier of nonvolatile field-programmable gate array (FPGA) technologies, today announced that the two companies have signed a global distribution agreement. This partnership complements Actel's existing distributor relationships and expands Actel's reach to customers seeking readily available, small-volume quantities. Customers can browse and purchase Actel's products through Mouser's printed catalog or directly from their website at http://www.mouser.com/actel . Later this month, Actel will also offer a "Buy Online" capability powered by Mouser on Actel's own website at http://www.actel.com/ .

Mouser's inventory includes the flash-based ProASIC3 and ProASIC Plus families, the antifuse-based MX, eX, SX-A and Axcelerator solutions, starter kits for the Actel Fusion, ProASIC3/E, ProASIC Plus and Axcelerator families, as well as the Silicon Sculptor3, FlashPro3 and FlashPro Lite programmers and adaptors.

"The ability to purchase smaller quantities of board-level components via credit card and start designing with them within 24-48 hours is quickly becoming a need, rather than a 'nice to have', for designers around the globe," said Dennis Kish, Actel senior vice president, sales and marketing. "Working with Mouser's efficient online global distribution capabilities, we can extend the availability of Actel's FPGAs, providing even more customers with solutions that deliver the power, security, reliability, and total system cost advantages they require."

"We're pleased to offer Actel's innovative FPGA products to our engineering customers for their new design projects," said Mike Scott, Mouser Vice President of Active and Passive Components. "We're also pleased to help Actel gain new customers and penetrate new markets through our innovative marketing programs."

According to Scott, the distribution agreement with Actel is in keeping with Mouser's unique business model of rapid introduction of the newest, most innovative products and the latest technologies, further enhancing the distributor's time-to-market advantage for their design engineering customers.

Mouser reaches a unique customer base of diverse business accounts that represent a wide range of small, medium and large companies, as well as individuals and consultants who recommend, specify and purchase board-level components for product designs that other distributors don't reach.

The distributor's broad-based product line, unsurpassed customer service, and streamlined warehouse operations make Mouser the design engineer's one- stop shop for all the board-level components and associated development tools necessary for total project design.

About Mouser

Mouser Electronics, Inc. is an electronic component distributor, focused on the rapid introduction of new products and technologies to electronic design engineers. Mouser.com features over 735,000 products online from more than 300 manufacturers. Mouser's 1,800+ page catalog is published every 90 days, providing designers with up-to-date data on the components now available for the next generation of electronic devices. Mouser ships globally to over 280,000 customers in 170 countries from its 432,000 sq. ft. state-of-the-art facility in Mansfield, Texas. For more information, visit http://www.mouser.com/ .

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit http://www.actel.com/. Telephone: 888-99-ACTEL (992-2835).

Trademarks

Mouser and Mouser Electronics are registered trademarks of Mouser Electronics, Inc. All other products, logos, and company names mentioned herein may be trademarks of their respective owners.

The Actel, Actel Fusion, ProASIC3/E, ProASIC Plus, Axcelerator, Silicon Sculptor3, FlashPro3 and FlashPro Lite names and logos are trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners.

Actel Corporation

CONTACT: Stephanie Mrus, Senior Manager, Public Relations of Actel
Corporation, +1-650-318-4614, or stephanie.mrus@actel.com; or Marketing
Communications Manager of Mouser Electronics, Inc., +1-817-804-3857, or fax,
+1-817-804-3803, or ellie.rovai@mouser.com

Web site: http://www.mouser.com/

Web site: http://www.actel.com/

11:19 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: hobby, mouser, fpga, actel |  Facebook |

14-11-06

NI Announces LabVIEW FPGA Digital and Communications System Design Pioneer Programs

Pioneer Devices Deliver Unprecedented Flexibility for Software-Reconfigurable Hardware

    NEWS RELEASE – Nov. 13, 2006 – National Instruments today announced pioneer programs for two new devices based on the NI LabVIEW FPGA Module, giving engineers and researchers early access to technology for digital and communications system design. Engineers now can use LabVIEW FPGA to write custom software for each device’s FPGA to prototype and test emerging standards or create custom protocols. With FPGA technology, engineers can repeatedly reconfigure hardware performance through software to meet next-generation requirements, which is a new approach to system design.

    “Virtual instrumentation revolutionized the test and measurement industry,” said Dr. James Truchard, NI president and CEO. “Graphical system design now raises the bar by supporting heterogeneous multiprocessing with combinations of multicore PCs and FPGAs. The communications pioneer program provides capabilities for building high-performance RF and communications test systems, while the digital pioneer program provides capabilities for a new generation of FPGA-based digital test systems.”

    The
    high-speed digital test pioneer device features the largest LabVIEW FPGA target to date. The product has four high-speed serial I/O lines up to 3.125 Gb/s and 24 general-purpose digital I/O lines up to 400 Mb/s. The PXI Express-based module offers a x4 connector for throughput rates up to 1 GB/s, ideal for streaming applications. The digital pioneer device extends the capabilities of the company’s current high-speed digital devices beyond 200 MHz clock rates to empower engineers to interface to DVI, HDMI, SATA, IEEE 1394 and other high-speed digital protocols requiring high throughput. The digital pioneer program includes the new high-speed digital device, a PXI Express chassis and controller, LabVIEW 8.20 Professional Edition and the LabVIEW FPGA Module.

    The
    communications pioneer device is a PCI board with two 14-bit IF input channels at 100 MS/s and two 14-bit IF output channels at 200 MS/s. The device features a LabVIEW FPGA target, making it ideal for software-defined radio and RFID applications. Engineers and researchers can perform digital upconversion and digital downconversion in hardware to alleviate bus bandwidth requirements and perform custom pulse shaping while still leaving the FPGA free for user-defined processing. The communications pioneer program includes the new communications device, LabVIEW, the LabVIEW FPGA Module and the Modulation Toolkit for LabVIEW.

    Through NI pioneer programs, engineers can preview technology before it is released to help with the design and functionality of the product. Readers can find out more about the new digital pioneer program by visiting
    www.ni.com/highspeeddigitalio/pioneer. Readers can learn more about the communications pioneer program by visiting www.ni.com/rf/pioneer.

    About National Instruments
    For 30 years, National Instruments (
    www.ni.com) has been a technology pioneer and leader in virtual instrumentation – a revolutionary concept that has changed the way engineers and scientists in industry, government and academia approach measurement and automation. Leveraging PCs and commercial technologies, virtual instrumentation increases productivity and lowers costs for test, control and design applications through easy-to-integrate software, such as NI LabVIEW, and modular measurement and control hardware for PXI, PCI, PCI Express, PXI Express, USB and Ethernet. Headquartered in Austin, Texas, NI has 4,000 employees and direct operations in nearly 40 countries. For the past seven years, FORTUNE magazine has named NI one of the 100 best companies to work for in America.

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22:12 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, dsp, labview, sdr, actel, rf |  Facebook |