27-06-07

Search Engine Market is booming

To show you the searchengine market is booming I share some of my "exotic" searchengines to you:

 

Hakia

http://www.hakia.com/


Accoona

http://www.accoona.com/


Powerset

http://www.powerset.com/


Squidoo

http://www.squidoo.com/

 
Sproose

http://www.sproose.com/

 
NosyJoe

 http://www.NosyJoe.com/


Bessed

 http://www.bessed.com/


ChaCha

http://www.chacha.com/ 


Mahalo

http://www.mahalo.com/Main_Page

19-06-07

Libero v8.0

I have just downloaded my copy of Libero Version 8.0. I have just started it for seeing the UI. The SmartDesign tool in the Libero IDE will be easy to use I think. Soon I will post here a small example on how to use it... I have other work to do at this time sorry guys ;-)

 

For the release notes see the following link: http://www.actel.com/download/software/libero/libero80rl....

 

 

A Project manager in Libero IDE whoohw!!!

 

SmartDesign will be amazing!

11:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: smartdesign, libero, actel, fpga, esl |  Facebook |

14-06-07

VHDL code for an 74-series ALU (the 74LS381 chip)

Hereby I give you my code of the 74LS381 IC, which is an ALU with 4-bits width.

 

The VHDL Code:

-- IC74381.vhd
-- Developed by Vincent Claes
-- claesvincent (at) gmail.com

-- http://mobile.skynetblogs.be
-- 2007 (c)
--
-- This version is a simlified version of the 74LS381 IC. It shows the main functionality in VHDL
-- It is developed for educational purposes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  s2  s1  s0  operation
--------------------------
--  L   L   L   clear
--  L   L   H   B minus A
--  L   H   L   A minus B
--  L   H   H   A plus B
--  H   L   L   A xor B
--  H   L   H   A + B
--  H   H   L   AB
--  H   H   H   PRESET  

entity IC74381 is
port(   a: in std_logic_vector (3 downto 0);
        b: in std_logic_vector (3 downto 0);
        s: in std_logic_vector (2 downto 0);
        f: out std_logic_vector (3 downto 0)
);
end IC74381;

architecture arch of IC74381 is
signal BminusA,AminusB,AplusB,AxorB,AandB,AB: std_logic_vector(3 downto 0);
signal au,bv0,bv1,bv2,bv3: unsigned(3 downto 0);
signal p0,p1,p2,p3,prod: unsigned(7 downto 0);

begin

BminusA <=  std_logic_vector(signed(b)-signed(a));
AminusB <=  std_logic_vector(signed(a)-signed(b));
AplusB  <=  std_logic_vector(signed(a)+signed(b));
AxorB   <= a xor b;
AandB   <= a and b;

au  <=unsigned(a);
bv0 <=(others=>b(0));
bv1 <=(others=>b(1));
bv2 <=(others=>b(2));
bv3 <=(others=>b(3));
p0  <="0000" & (bv0 and au);
p1  <="000"&(bv1 and au) & "0";
p2  <="00" & (bv2 and au) & "00";
p3  <="0" & (bv3 and au) & "000";
prod<=((p0+p1)+(p2+p3));
AB<=std_logic_vector(prod(3 downto 0));

f   <=  "0000"      when s="000" else
        BminusA     when s="001" else
        AminusB     when s="010" else
        AplusB      when s="011" else
        AxorB       when s="100" else
        AandB       when s="101" else
        AB          when s="110" else
        "1111"; 
end arch;

 

 

The testbench code:

 

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    a : inout std_logic_vector(3 downto 0) := x"7";
    b : inout std_logic_vector(3 downto 0) := x"3";
    s : inout std_logic_vector(2 downto 0));

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 10 ns;
    s <= "101";
    wait for 10 ns;
    s <= "110";
    wait for 10 ns;
    s <= "111";
    wait for 10 ns;
    s <= "000";
    wait for 10 ns;
    s <= "001";
    wait for 10 ns;
    s <= "010";
    wait for 10 ns;
    s <= "011";
    wait for 10 ns;
    s <= "100";
    wait for 20 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.numeric_std.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal a : std_logic_vector(3 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal s : std_logic_vector(2 downto 0);
  signal f : STD_LOGIC_VECTOR(3 downto 0);

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (a => a,
              b => b,
              s => s);

  -- Instantiation of Model Under Test.
  IC74381_0 : entity work.IC74381
    port map (a => a,
              b => b,
              s => s,
              f => f);
end tbGeneratedCode;

 

Screenshot of the Simulation in ModelSim:

 

wave_IC74381

 

Please remember this code is written in 4bits width. And I show the results in HEX!!!

 

For educational purposes I also include the netlist view of my program:

 

netlistview_IC74381

 

13-06-07

VHDL Even parity Detector (A simple example of VHDL for learning Hardware Programming languages)

Here is the VHDL code (since the VHDL language is selfdescriptive I will not put comments in it :-) )

 

-- Even_Parity.vhd
library ieee;
use ieee.std_logic_1164.all;

entity even_parity is
 port(
  input: in std_logic_vector(2 downto 0);
  output: out std_logic
  );
end even_parity;

architecture arch of even_parity is
 signal s1,s2,s3,s4: std_logic;

begin
output  <= (s1 or s2) or (s3 or s4);
s1      <= (not input(2)) and (not input(1)) and (not input(0));
s2      <= (not input(2)) and input(1) and input(0);
s3      <= input(2) and (not input(1)) and input(0);
s4      <= input(2) and input(1) and (not input(0));

end arch;

 

Here is the code for a simple testbench:

 

-- Generated by WaveFormer Lite Version 11.11d at 12:44:17 on 6/13/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       input

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    input : inout std_logic_vector(2 downto 0) := "000");

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 150 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
  begin
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    input <= "001";
    wait for 10 ns;
    input <= "010";
    wait for 10 ns;
    input <= "011";
    wait for 10 ns;
    input <= "100";
    wait for 10 ns;
    input <= "101";
    wait for 10 ns;
    input <= "110";
    wait for 10 ns;
    input <= "111";
    wait for 10 ns;
    input <= "000";
    wait for 10 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal input : std_logic_vector(2 downto 0);
  signal output : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (input => input);

  -- Instantiation of Model Under Test.
  even_parity_0 : entity work.even_parity
    port map (input => input,
              output => output);
end tbGeneratedCode;

 

I used the Libero IDE from ACTEL corporation to get my FPGA (ProASIC3) programmed. This IDE includes the synplify synthesis tool to get the code translated.

 

I used the ModelSim Actel Edition 6.1f to simulate the design. Here you find a screenshot of the simulation:

 

even_detector

13:13 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: synplify, fpga, libero ide, example, modelsim, vhdl, hardware, programming, actel, actl |  Facebook |