27-03-07

R&D in Europe is not healthy

R&D paradigm shifting

An ongoing debate in Europe concerns the creation of the European Institute of Technology (EIT).

The EIT, a consolidated mega research center that would house both academic and industry projects, keep talent in the EU, and unite researchers in the 27 member states under the EU flag, may well end up being a reality in Brussels. Yet the EIT proposal from the European Commission continues to go through revisions, and the concept has many critics. All of this points to a bigger issue: Europe is headed toward an R&D crisis.

Europe has long been second in annual R&D spending to the leader, the United States, and in some sectors has fallen behind third-place Japan. Now Europe is facing new and strong forces in Asia when it comes to R&D.

According to a 2006 study on global R&D by the Battelle Memorial Institute, China has increased R&D spending annually about 17% over a 12-year period, compared to 4% to 5% for Europe and the United States. As China and India pour money into R&D, offer their cheap skilled labor, and grow their vibrant economies, both countries could move into the top tier of R&D spenders worldwide.

Moreover, R&D investment in Asia is accelerating. The Battelle report surveyed global businesses and asked if the companies planned to increase R&D in Europe in 2007. About 28% said yes, and 48% said no. When asked if they planned to increase R&D in Asia, the response was 65% yes, and 10% no.

"Now we recognize that China and India are challenging us, and that's the main reason this discussion has become much more intensive," says Esko Aho, former prime minister of Finland, who last year released an influential report on innovation in Europe.

"Europe is moving too slowly, and this can lead to a crisis when we are hit by a demographic revolution and its consequences."

At first glance, an R&D crisis seems strange. Europe has many world-class research institutes: IMEC in Belgium, Fraunhofer in Germany, and VTT in Finland, to name only a few. Livio Baldi, director of R&D cooperative programs for STMicroelectronics, calls it the European paradox: lots of world-class research pockets but a poor track record of commercializing the results.

"Europe has a lot of publications but very few patents and startups," he says.

Part of the problem is fragmentation. Pockets of research are not linked to a central hub, something the EIT is intended to resolve. Another issue has been talk instead of action. Europe's "Lisbon Strategy," a grand development plan launched in 2000, promised to reshape the EU into the "most competitive and dynamic knowledge-based economy in the world" by 2010. Targets for increasing R&D spending in member states were set but not met.

At a deeper level, cultural issues are to blame. Europe's risk-averse culture limits entrepreneurial drive, and organizational structures work to lock people in their place.

"We have no tradition of people moving from academia to government to business and back," Aho says. "Innovation required that type of mobility."

Aho says he believes that the proposed EIT could be a small part of a more comprehensive solution. Among the recommendations in his report was fundamental cultural change that would encourage mobility and promote more entrepreneurial risk taking.

Jules Duga, coauthor of the Battelle report, says that what is happening in Europe is merely early signs of a gradual but enormous rearrangement in global technology dominance due to the rise of Asian giants.

"Countries will have to determine their strengths, rearrange resources, and adjust over a period of time to a changing position in R&D on a global basis," Duga says. "Expect a shift in the overall R&D paradigm."

Source: Battelle Memorial Institute and R&D Magazine’s 2007 Global R&D Report

21-03-07

Success with IMEC and Synplicity's Synplify® Premier Software

 
 

 


Success with IMEC and Synplicity's Synplify® Premier Software
Click here to learn more about the Synplify Premier tool.

 
IMEC, a European nanoelectronics research institution, used Synplify Premier software from Synplicity to demonstrate that its C-programmable reconfigurable processor architecture ADRES is feasible for use in portable wireless multimedia devices. The entire processor system was successfully prototyped for a multimedia ADRES processor instance on a Xilinx Virtex-4 FPGA through use of the Synplify Premier tool. The Synplify Premier product provided excellent support for achieving the required clock frequency. IMEC credits the Synplify Premier tool's built-in knowledge of the FPGA's physical characteristics for the accurate timing results that it delivers. The ADRES prototype system has been important for IMEC in showing that the ADRES processor architectural template and its corresponding C-compiler are sufficiently stable for use in portable devices. 
 
 
IMEC's ADRES Innovation Promises a New Future for Hand-held Multimedia Devices
 
IMEC of Leuven, Belgium is one of the world's leading independent research institutions in nanoelectronics and nanotechnology. Its research focuses on next generation chips and systems, and bridges the gap between university research and technology development in industry. IMEC's blend of know-how and corporate relationships position the organization to help shape key technologies for future systems. 
 
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) contains two views which are tightly coupled: an array of processing elements that runs the data flow part of the application and a VLIW that executes the control. For hand-held multimedia devices, this technology delivers enormous flexibility benefits over fixed ASICs because various video codec standards can be quickly and easily accommodated through C programming. In addition, ADRES-based processors offer power efficiencies six to twelve times higher than state-of-the-art C-programmed processors. 
 
With the demonstration IMEC has proven that processors based on the ADRES architecture can deliver sufficient performance. The multimedia ADRES processor instance was developed to support MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. The demonstration employed the HAPS-32 from HARDI Electronics, which contains two Xilinx Virtex-4 LX200 FPGAs, as its prototyping board. IMEC constrained the FPGA clock input to 50 MHz to decode 30 frames/sec of H.264/AVC content at CIF resolution. 
 
Synplify Premier Tool Delivers the Necessary Performance 
 
IMEC began by synthesizing the design using the Synplify Pro product from Synplicity, the tool that had served the organization well for many years. Synplify Pro software came close to the goal at 46 MHz, but not close enough. 
 
"It was essential that we find a way to reach 50 MHz, and so we performed an investigation of the state of the art in FPGA synthesis," said Maryse Wouters, Activity Leader of the Integration Team. "Fortunately we found our answer, the Synplify Premier solution, which is capable of delivering the performance we needed. In fact it did even better than we had hoped, 52.6 MHz. Everyone was pleased with the performance gain."
 
"The reason why the Synplify Premier tool does the job better is that it understands the physical characteristics of the FPGA in fine detail and uses that knowledge to craft an optimal design," explained Wouters. "That's particularly important with the most advanced FPGAs on the market." 
 
Building on Synplify Pro technology, the Synplify Premier solution embodies its knowledge of an FPGA's specifics through a patented Synplicity technique called graph-based physical synthesis, which represents an FPGA's pre-existing wires, switches, and placement sites as a detailed routing resource graph. Graph-based physical synthesis produces rapid timing closure by automatically outputting timing-correlated legal placement and by considering availability of actual FPGA routing resources when measuring delays, rather than just physical proximity of instances. Unlike ASICs, in an FPGA physical proximity does not always correlate to timing delays, making ASIC-style physical synthesis approaches inaccurate when applied to FPGAs. Only graph-based physical synthesis can accurately estimate timing delays when performing physical synthesis.   
 
Graph-based physical synthesis also cut place-and-route runtimes significantly for IMEC. The total elapsed time for placement and routing was six hours with the Synplify Premier solution versus seventeen hours with the Synplify Pro tool. The reason is that in addition to performing synthesis, the Synplify Premier product actually places the design in a manner known to meet timing, and delivers a design that will be fully routable using the Xilinx ISE toolset. 
 
The correlation between the Synplify Premier solution's performance predictions and actuals was much better than IMEC had seen. The new tool predicted 51 MHz performance, which was very close to the actual result of 52.6 MHz.
 
IMEC's New Standard for Synthesizing 90 nm FPGAs and Below
 
With its flexibility to incorporate multiple video codec standards, the short time-to-market made possible by its high level language programmability, and its power efficiency, ADRES promises to play a major role in the next generation of mobile multimedia platforms. 
 
"Using an FPGA-based prototype platform, IMEC has demonstrated its C-programmable multimedia ADRES processor instance for real time H.264/AVC video decoding," said Wouters. "The performance gain that the Synplify Premier solution delivered was as promised in the Synplify Premier data sheet." 
 
Because of the excellent results it delivers, the Synplify Premier product has now become part of the tool flow at IMEC for future projects using leading edge FPGAs. "It is clear that for 90 nm FPGAs and beyond, the timing closure offered by the Synplify Premier tool is crucial," Wouters concluded. 
 
Click here to learn more about the Synplify Premier tool.

19-03-07

Thursday 22/03/2007: "Analog meets Digital on snow" seminar

Thursday there is a ACAL (ACTEL representative for Belgium) seminar planned. Here are the topics that will be handled:

 

Agenda :
        08:30 - 09:00 : Registration + Breakfast
        09:00 - 09:05 : Welcome (Guy Maertens MD Acal Belgium)
        09:05 - 11:00 : Power (Jens Hedrich FAE Linear Technology)
        11:00 - 11:15 : Coffee Break
        11:15 - 12:00 : Data Conversion (Jens Hedrich FAE Linear Technology)
        12:00 - 13:00 : Bruegelian Buffet
        13:00 - 13:15 : Igloo Launch (Vaughan Price Managing Director Actel Europe)
        13:15 - 13:45 : New Technology Solutions (Patrizio Piasentin Regional Sales Manager Actel)
        13:45 - 14:30 : System Management, µTCA, MotorControl (Luca Cattaneo ETM Actel)
        14:30 - 14:45 : Coffee Break
        14:45 - 15:30 : Low Power Design Tricks (Luca Cattaneo ETM Actel)
        16:00 - 18:00 : Ski & Snowboard Session + Snacks
        18:15 - 19:00 : Appetizers and Prize Giving

 

More information can be found here:

http://www.acal.be/index.php?module=calendar&calendar...

22:01 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: acal, actel, snow, fpga, actel europe |  Facebook |

 

Actel and ARM Develop High-Performance 32-Bit Processor Optimized for FPGAs

Actel Offers New Cortex-M1 for Use in Flash-based M1 ProASIC3 and M1 Fusion Devices

MOUNTAIN VIEW, Calif., March 19, 2007 — Disclosing further details of its industry-standard processor portfolio, Actel Corporation (NASDAQ: ACTL) today announced the availability of its implementation of the ARM® Cortex™-M1 processor, a small, high-performance, 32-bit soft core co-developed by the companies for optimal use in field-programmable gate arrays (FPGAs). Removing the license and royalty fees typically associated with licensing models for industry-leading processor cores, Actel offers free access to advanced ARM processor technology to the broad marketplace. The free delivery of the Cortex-M1 processor for use in Actel's flash-based, M1-enabled Actel Fusion and ProASIC3 FPGAs provides system designers programmable flexibility and system-level integration, enabling the development of low-cost, high-performance systems.

"With the significant increase in the use of FPGAs as flexible, cost-effective platforms for the rapid design of high-quality embedded systems, the introduction of an FPGA-optimized ARM processor enables us to serve the growing needs of companies who require highly programmable solutions," said John Cornish, vice president, marketing, Processors Division, ARM. "The unprecedented security benefits and advanced features offered by Actel's flash-based FPGAs make these devices an ideal vehicle for our high-performance processor technology."

Rich Brossart, vice president, product marketing at Actel, added, "Evidenced by the success of our soft ARM7™ family processor core, designers continue to show great interest in implementing industry-standard 32-bit processor technologies in FPGAs. With the addition of the FPGA-optimized ARM Cortex-M1 processor, free of license and royalty fees, to our broad processor portfolio, system designers can select the solution that best meets their design requirements regardless of application or volume."

Cortex-M1 Processor and Actel's M1-Enabled FPGAs

Derived from ARM's three-stage Cortex-M3 processor pipeline, the highly configurable Cortex-M1 processor operates at up to 72 MHz in Actel's M1-enabled Fusion Programmable System Chip (PSC) or ProASIC3 FPGAs. Providing a good balance between size and speed for embedded applications, the core is able to be implemented in as few as 4300 tiles, roughly 20 percent of an M1A3P1000 ProASIC3 device or 30 percent of a mixed-signal M1AFS600 Actel Fusion PSC. The Cortex-M1 processor solution also connects to the industry-standard AHB bus, allowing designers to build a subsystem and easily add peripheral functionality to the processor.

With the increasing costs of application-specific integrated circuit (ASIC) design, designers can benefit from a Cortex-M1 processor-based implementation in an FPGA due to reduced design time and a lower cost of entry into system-on-chip design, particularly for lower volume applications. However, for designs that scale to ultra-high volumes, the 32-bit Cortex-M1 processor runs the industry-standard Thumb® instruction set and is upward compatible with the Cortex-M3 processor, providing an easy migration path to ASIC implementation.

Actel's flash-based FPGAs, the mixed-signal M1 Actel Fusion PSCs and low-cost M1 ProASIC3 devices, are virtually immune to tampering, assuring users that valuable IP will not be compromised or copied. The single-chip devices also provide the low power, firm-error immunity and live at power-up capabilities that are inherent to all Actel FPGAs.

Comprehensive Tool Support

The Cortex-M1 processor is supported by the comprehensive tools and knowledge that currently exists for the ARM architecture, far surpassing the level of support offered for proprietary processors. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment, and Actel Libero Integrated Design Environment—all available for free download from Actel's Web site. Actel's implementation of the Cortex-M1 processor is fully supported by the ARM RealView® Development Suite and RealView Microcontroller Development Kit. Third-party vendors, such as Aldec, CriticalBlue, CodeSourcery, IAR, ImpulseC and Keil™, an ARM Company, will also support the new processor with a host of tools—from compilers and debuggers to RTOS support.

Pricing and Availability

Actel's implementation of the Cortex-M1 processor will be available for early access in April. The M1A3P1000 ProASIC3 device and M1AFS600 Fusion PSC device will sample in Q3 2007 with production quantities in Q4 2007. Pricing for the M1 devices starts at $3.95. For further information about pricing and availability, please contact Actel or visit the company's Web site at www.actel.com .

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).

21:50 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, arm, 32-bit, softcore, core, ip, processor, actel, cortex-m1 |  Facebook |

ARM Extends Cortex Family With First Processor Optimized for FPGA

ARM Extends Cortex Family With First Processor Optimized for FPGA

The ARM Cortex-M1 processor enables OEMs to reduce development costs throughstandardization on a single architecture across FPGA, ASIC and ASSP

CAMBRIDGE, UK, March 19, 2007 — ARM [(LSE:ARM); (Nasdaq: ARMHY)] today announced the availability of the ARM® Cortex™-M1 processor – the first ARM processor designed specifically for implementation on FPGAs. The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers.

ARM and Actel will both be demonstrating the Cortex-M1 processor at the Embedded Systems Conference in San Jose, Calif., April 2-5.

The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor. The Cortex-M1 processor is supported by leading FPGA synthesis vendors, software development tools, and real-time operating systems, giving FPGA designers unprecedented choice and flexibility.

"Gartner Dataquest maintains that FPGAs/PLDs have a very bright future," said Bryan Lewis, research vice president, Gartner Dataquest. "We expect solid growth (15.7 percent) to resume in 2008 and forecast the FPGA/PLD market to outperform semiconductors from 2008 onward."1
"The Cortex-M1 processor extends the reach of the ARM architecture in the FPGA domain, and advances our goal of providing processor solutions for the entire digital world," said Graham Budd, EVP and general manager, Processor Division, ARM. "By leveraging ARM's vast installed user base in the ASIC/ASSP and microcontroller markets, along with support from our own RealView® family of tools as well as product support from the ARM Connected Community, the Cortex-M1 processor will deliver significant savings to OEMs in terms of software development resources, tools, and training."

Actel has licensed the Cortex-M1 processor and will make it available at no additional cost to their customers. The FPGA-optimized Cortex-M1 processor offers users of Actel's flash-based M1-enabled Actel Fusion Programmable System Chips and ProASIC3 FPGAs a compact and efficient processor satisfying the requirements of a wide range of end applications. Actel will support the Cortex-M1 processor with its CoreConsole IP Deployment Platform, its SoftConsole program development environment and Actel Libero Integrated Design Environment – all available for free download from Actel's website.

"Following the success of our ARM7™ family-based solutions, Actel worked closely with ARM to optimize its Cortex-M1 processor for FPGA implementation from the ground up, making it an extremely valuable addition to our growing processor library," said Rich Brossart, vice president, product marketing, Actel. "Free of the contract negotiations and fees typically associated with industry-standard processor cores, Actel will make the Cortex-M1 processor available to those companies who desire highly programmable solutions regardless of application or volume."

Tools and Peripherals Support

The Cortex-M1 processor will be fully supported by forthcoming releases of the ARM RealView® Development Suite and RealView Microcontroller Development Kit. The RealView Development Suite will include a complete instruction set system model (ISSM) allowing developers to create and test applications for the Cortex-M1 processor out of the box. Developers can easily customize the RealView Development Suite's debugger to visualize and interact withperipherals added around a Cortex-M1 processor, and will also be able to connect and debug applications running on Cortex-M1 silicon using ARM's high-performance RealView ICE and ULINK®2 run control units.

System performance and design turn around time are boosted further with ARM AMBA® compliant PrimeCell® peripheral IP, including ARM's latest ultra-efficient microDMA (PL230).
ARM Connected Community Partners, including CodeSourcery, Express Logic, IAR Systems, Mentor Graphics Inc., Micrium and Synplicity will all support the Cortex-M1 processor. For improved flow integration, the Cortex-M1 processor deliverables will include an IP description conforming to the IP-XACT standard from The SPIRIT Consortium.

Low area, high frequency and ease of use

The ARM Cortex-M1 processor is a streamlined three-stage 32-bit RISC processor that implements a subset of the popular, high density Thumb®-2 instruction set. This enables both the processor and software footprint to meet the area budget of the smallest FPGA devices, while retaining compatibility with Thumb code for any ARM processor from the ARM7TDMI® processor upwards.The Cortex-M1 processor is capable of more than 170 MHz, whilst occupying less than 15 percent area of popular low-cost FPGA devices. Despite being the smallest processor in the Cortex family, the Cortex-M1 processor can deliver 0.8 DMIPS/MHz. Typical applications for the Cortex-M1 processor on FPGAs include embedded control, communications, networking and aerospace.

More information on ARM solutions in FPGA is available from www.arm.com/fpga.

Availability

Free of license and royalty fees, Actel's implementation of the Cortex-M1 processor will be available for early access in April via the Actel website www.actel.com. The M1-enabled ProASIC3 and Actel Fusion PSC devices will sample in Q3 2007.

The ARM Cortex-M1 processor RTL and associated EDA views optimized for a range of FPGA vendor devices including Actel, Altera, Lattice and Xilinx will be available for license by OEMs in 2Q'07.

About the ARM Cortex Family of Processors

The three series in the ARM Cortex family enable chip manufacturers and OEMs to standardize around a single architecture from low-end microcontrollers to high-performance applications processors. Featuring Thumb-2 technology, the ARM Cortexfamily significantly reduces development costs and increases enterprise efficiency.

  • ARM Cortex-A Series: Applications processors for complex OS and user applications
  • ARM Cortex-R Series: Embedded processors for real-time systems
  • ARM Cortex-M Series: Deeply embedded processors optimized for microcontroller and low-cost applications

About ARM
ARM designs the technology that lies at the heart of advanced digital products, frommobile, home and enterprise solutions toembedded and emerging applications. ARM's comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphics processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.

About the ARM Connected Community
The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions. For more information, please visit http://www.arm.com/community.

ENDS

1. Gartner, Inc., "Forecast: ASIC/ASSP, FPGA/PLD and SLI/SOC Applications, Worldwide, 2002-2010 (4Q06 Update)", by John Barber and Bryan Lewis, December 4, 2006.

ARM, Thumb, RealView, PrimeCell and ARM7TDMI are registered trademarks of ARM Limited. Cortex and ARM7 are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; and ARM Physical IP, Inc.; and ARM Norway AS.

Contact: Stephanie Mrus, Actel Corporation, 650.318.4614

21:49 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, fpga, actel, cortex-m1, oem |  Facebook |

17-03-07

ACTEL FPGA developers community

I just opened the ACTEL FPGA developers community which is a mailinglist of all Actel FPGA developers. It will be a meeting place from ACTEL FPGA developers all over the world. If you would like to know where people are working on with ACTEL fpga's just join the mailinglist.

 

 

 

Bètaversie van Google Discussiegroepen
ACTEL FPGA developers
Naar deze groep gaan

 

 

 

Bètaversie van Google Discussiegroepen
Aanmelden bij ACTEL FPGA developers
E-mailadres:
Naar deze groep gaan

14:34 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, developers, community, fpga |  Facebook |

16-03-07

VHDL code for 7segment display

For some of your FPGA projects it can be usefull to get an 7-segment display driver circuit. There is no 7-segment LCD on my ACTEL fpga boards but I am sure you guys know how to work around this topic with your hands ;-)

 

 

VHDL code listing:

 

LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY seg7 ISPORT (
D       : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);  -- BCD input      
S       : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- 7 segment outputsEND seg7;
ARCHITECTURE display OF SEG7 ISBEGINs <=  	"1000000" WHEN d = "0000" ELSE       
      	"1111001" WHEN d = "0001" ELSE       
	"0100100" WHEN d = "0010" ELSE       
	"0110000" WHEN d = "0011" ELSE       
	"0011001" WHEN d = "0100" ELSE       
	"0010010" WHEN d = "0101" ELSE       
	"0000010" WHEN d = "0110" ELSE       
	"1111000" WHEN d = "0111" ELSE       
	"0000000" WHEN d = "1000" ELSE       
	"0010000" WHEN d = "1001" ELSE       
	"0001000" WHEN d = "1010" ELSE       
	"0000011" WHEN d = "1011" ELSE       
	"1000110" WHEN d = "1100" ELSE       
	"0100001" WHEN d = "1101" ELSE       	
	"0000110" WHEN d = "1110" ELSE       
	"0001110";                     
END display;

13:05 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (2) | Tags: fpga, vhdl, actel, 7-segment |  Facebook |

12-03-07

FPGA based arcadegame Frogger

 

 

Link: http://www.youtube.com/watch?v=hkL3hWZxeTk

22:12 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: fpga, frogger, arcade game |  Facebook |

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

Link: http://www.fpgajournal.com/news_2007/03/20070312_03.htm

Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of CoVer™, a Windows®-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7™ core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance

Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop

The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

Components

The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

* Aldec Active-HDL (Designer Edition) mixed-language simulator
* Actel’s CoreConsole IP Deployment Platform
* Actel Libero® Integrated Design Environment (IDE) – Gold edition
* Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
* Software development system, including Actel’s SoftConsole program development environment

Availability

CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor sales@aldec.com.

About Aldec

Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. Additional information on Aldec and all its products can be found at www.aldec.com.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com.

CoVer and Active-HDL are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

22:09 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: arm, actl, co-verification, actel, fpga, hw sw, asic, vhdl |  Facebook |

Arasan Chip Systems Extends USB IP Offerings to Actel’s CompanionCore Program

Source: http://www.fpgajournal.com/news_2007/03/20070306_02.htm

 

SAN JOSE, Calif.--(BUSINESS WIRE)--Arasan Chip Systems, Inc. (“Arasan”), a leading supplier of reusable intellectual property (IP) cores, semiconductors and design services, today announced that it has joined Actel Corporation’s CompanionCore Alliance Program. Arasan has optimized its USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores for use with Actel’s flash-based, single-chip Actel Fusion, IGLOO, ProASIC3/E and ProASIC Plus field-programmable gate arrays (FPGAs). With these USB IP offerings, system designers have access to proven building blocks to streamline design and development, shorten time to market and reduce design costs and risks.

Actel CompanionCore products offer seamless implementation through Actel's suite of internal and third-party EDA development tools, documentation, and quality service and support, thereby streamlining the design process. Specific FPGA target data is available for each IP core on the CompanionCore Web site at http://www.actel.com/products/partners/companioncore/.

“We are excited about the opportunity to partner with Actel in its CompanionCore program,” said Kevin Walsh, vice president of marketing at Arasan Chip Systems. “Our customers can confidently use these USB cores, and others that we intend to put into the program, knowing we have done all the work to optimize them for use in Actel’s FPGAs.”

Rich Brossart, Actel vice president, product marketing said, "Arasan’s USB IP solutions complement Actel's flash-based devices, including the company’s innovative Actel Fusion, IGLOO, and ProASIC3/E FPGAs. For customers requiring USB connectivity, the addition of Arasan’s USB 2.0 Host, 2.0 Hub, 2.0 Device and OTG cores to the Actel CompanionCore program will enhance designer productivity and versatility while reducing time to market."

Total Technology Solution

Arasan provides a total technology solution to all its licensees, including IP source code, a test environment, sample device drivers, synthesis scripts, and complete technical documentation. The total technology solution also includes optional product design development tools like the hardware validation platform and software targeted for Linux. Custom bus integration services are offered to integrate the IP in a customer specific manner. Available for purchase, Arasan’s validation platform is a stand-alone board used to ease compliance testing of as well as prototyping, including driver development.

Pricing and Availability

Licenses for the USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores are available from Arasan in either synthesizable RTL or Actel-targeted netlist formats. The USB cores are available under special license terms. For more information on these IP cores, please visit Arasan at http://www.arasan.com or Actel at http://www.actel.com/products/ip/.

About Arasan

Arasan Chip Systems Inc. founded in 1995, is a leading supplier of Reusable Intellectual Property (IP’s) cores, semiconductors and electronic design services. Arasan’s product portfolio is focused on Bus Interfaces and includes IP’s for USB 1.1 & 2.0, PCI, SDIO and CE-ATA technologies. Arasan’s products and services enable businesses to develop and leverage product design and development. Arasan Chip Systems has been an executive member of SD Card Association since 2001, MMCA since 2003 and CE-ATA since 2004. Arasan is headquartered in San Jose, California, with design centers in India and support options available in Taiwan, China & Europe. Licensees of Arasan’s USB IP include companies like TI, Cisco, NEC, Staccato, Los Alamos National Laboratory, and General Atomics.

Visit: www.arasan.com for more product information.

03-03-07

Research in motion (From US and Europe to Asia)

Today I received my copy of the new EuroAsia Semiconductor magazine (if you are interested check out; http://www.euroasiasemiconductor.com.

 

The first page from this magazine was a so true story about the move of the Semiconductor Research... if I made you curious you can read it online at http://www.euroasiasemiconductor.com/news_full.php?id=7829

 

10:31 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: euroasia, semiconductor, research |  Facebook |

02-03-07

Binary Counter on ACTEL ProASIC3 FPGA by use of CoreABC

I have just created a binary counter on the CoreABC softcore from ACTEL (see code below). Create the project from coreconsole (CoreABC, CoreGPIO and CoreAPB) in the latest post on this blog and put the next lines of code into the softcore. enjoy it!

 

 

// Created by Vincent Claes

// If you want to use please add a comment on my blog

// http://mobile.skynetblogs.be

   

    JUMP $Main

$Main
    WAIT WHILE INPUT0
$LedOff   
    LOAD 0
$LedOn
    APBWRT ACC 0 0
    INC
    CALL $Wait500ms
    JUMP $LedOn  
    CALL $Wait500ms
    JUMP $LedOff

$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN

22:37 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: actel, fpga, coreabc, coregpio, coreapb, binary counter, proasic3 |  Facebook |

Blinking leds by use of CoreABC, CoreGPIO and CoreAPB

According to the technical contacts I have within ACTEL it is not possible at this time to write the value you have in the accumulator to the parallel outputs on the softcore (CoreABC). In order to do something like this you have to experiment like me with the following cores in your coreconsole: CoreABC, CoreGPIO and CoreAPB.

 

Check out my set-up in coreconsole:

CoreABC_CoreGPIO_CoreAPB

The program I have placed into the hard-tiles of the CoreABC are the following lines:

 
    JUMP $Main

$Main
    WAIT WHILE INPUT0
$LedOff    APBWRT DAT 0 0 1
    CALL $Wait500ms
$LedOn    APBWRT DAT 0 0 3
    CALL $Wait500ms
    JUMP $LedOff
$Wait500ms
    CALL $Wait100ms
$Wait400ms
    CALL $Wait100ms
$Wait300ms
    CALL $Wait100ms
$Wait200ms
    CALL $Wait100ms
$Wait100ms
    CALL $Wait20ms
$Wait80ms
    CALL $Wait40ms
$Wait40ms
    CALL $Wait20ms
$Wait20ms
    CALL $Wait10ms
$Wait10ms
    NOP
    LOADLOOP 34998
$Wait10msInner
    DECLOOP
    JUMP IFNOT LOOPZ $Wait10msInner
    RETURN
 
 
With thanks to ACTEL corporation for bringing us the CoreABC softcore processor and example 1 of this great softcore
 
Here we use the CoreABC processor as it is designed for... being a Master on the APB bus on our ACTEL fpga. the CoreGPIO is a slave core on this APB bus.
 
I implemented this program on my ProASIC3 A3P250 PQ208ES 0539 FPGA and the board I used for this is the A3PE-A3P-EVAL-BRD1 REV3.
 
Enjoy this sample.....
 

21:40 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: coreabc, actel, coregpio, coreapb, proasic3 |  Facebook |

LinuxLink Radio – Podcast for Embedded Linux Developers

Timesys launches a new rss feed that provides you with the newest podcast for embedded linux developers.

 

Check out this link and have a nice time listining to those coverages of diverse embedded linux subjects.

 

Hopefully there will be one day a podcast concerning embedded linux for FPGA projects ;-)

08:54 Gepost door Mobile blogger in Algemeen | Permalink | Commentaren (0) | Tags: embedded, linux, fpga, timesys, podcast |  Facebook |